Data output circuit in combined SDR/DDR semiconductor memory...

Details Data output circuit in combined SDR/DDR semiconductor memory... Data output circuit in combined SDR/DDR semiconductor memory...

2005-03-22

2005-03-22

Tan, Vibol (Department: 2819)

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

C365S201000, C365S233100

Reexamination Certificate

active

06870776

ABSTRACT:
A data output circuit includes first, second, third, and fourth data latches, and first and second data output drivers. The first, second, third, and fourth latches generate first pull-up signals, second pull-up signals, first pull-down signals, and second pull-down signals, respectively. In DDR mode, first and third latches latch even data in response to an even clock, while second and fourth latches latch odd data in response to an odd clock. In SDR mode, first and third latches latch first data in response to a data output clock, while second and fourth latches latch second data in response to the data output clock. The first and second data output drivers drive a first and second output pad, respectively, to predetermined voltages in response to the pull-up signals and the pull-down signals. The data output circuit reduces the number of data buffers, reducing the size of a semiconductor memory device.

REFERENCES:
patent: 6208582 (2001-03-01), Kanda et al.
patent: 6549470 (2003-04-01), Hardee et al.
patent: 6556492 (2003-04-01), Ernst et al.
patent: 2001-67870 (2001-03-01), None
patent: 1999-0037555 (1999-05-01), None
English Language of Abstract of Korean Patent Publication No. 1999-0037555.
English Language of Abstract of Japanese Patent Publication No. 2001-67870.

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