Data output circuit for semiconductor memory device

Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch

Reexamination Certificate

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Details

C365S189020, C365S230020, C365S191000, C365S198000

Reexamination Certificate

active

07948808

ABSTRACT:
The present invention relates to a semiconductor memory, and more specifically, to a data output circuit capable of differentiating global data lines in accordance to an operation mode to output them to a data input/output pin. The present invention includes: a multiplexer selecting any one of a plurality of global input/output lines which can receive variable data bandwidth directed by control signals and which can output data carried on the selected global input/output line, and a controller generating the control signals in accordance to operation mode signals corresponding to a data bandwidth and address signals provided for selecting data and providing them to the multiplexer. Thereby, the present invention can realize an improved data read speed by reducing the loading of the global input/output line.

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patent: 1020050052725 (2005-06-01), None

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