Data output circuit for a dynamic memory

Details Data output circuit for a dynamic memory Data output circuit for a dynamic memory

1985-11-04

1988-01-12

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

365190, G11C 700

Patent

active

047195959

ABSTRACT:
There is disclosed a data output circuit with a nibble mode function for a dynamic memory. The data output circuit comprises a plurality of data output control circuits provided in correspondence with a plurality of paired data transfer nodes. Each pair of transfer nodes is connected to the corresponding memory array and receives data stored in a designated memory cell of the memory cell.

REFERENCES:
patent: 4397000 (1983-08-01), Nagami
patent: 4602353 (1986-07-01), Wawersig et al.
patent: 4603403 (1986-07-01), Toda
Patent Abstracts of Japan, vol. 5, No. 177, Nov. 13, 1981, concerning Japanese Patent Document No. 56-107385.
Japanese Patent (Kokoku) No. 58-10799, N. Kitagawa et al., (2/28/83).

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