Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch
Reexamination Certificate
2000-08-11
2001-09-18
Nguyen, Tan T. (Department: 2818)
Static information storage and retrieval
Read/write circuit
Having particular data buffer or latch
C365S203000
Reexamination Certificate
active
06292405
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to integrated digital systems, and, more particularly, to a data output buffer for an integrated digital system having low noise characteristics, especially for CMOS integrated devices and static memories. The data output buffer provides for high speed transitions to meet stringent speed performance requirements.
BACKGROUND OF THE INVENTION
Many integrated digital systems that process and/or handle digital data streams are provided with an array of output buffers for driving the lines of a data bus. The data output buffers are to prevent undesired electrical interactions between the source of the data to be made available external the system, and the driven external circuitry.
In view of the relatively large capacitance of the driven external circuitry, the peak of current absorbed from the supply rails upon the switching between logic states may cause a switching noise on the supply rails. The switching noise may be due to an unavoidable resistive drop, and may effect sensitive data processing circuits that are upstream of the output buffers.
The supply voltage is commonly generated and regulated externally and applied to the integrated circuit. The supply voltage within the integrated circuit may be subject to variations due to internal resistive drops proportional to the absorbed current, and to inductive effects inversely proportional to the rise time of the step function of absorbed current. Both of these effects contribute to the supply noise.
Switching noise is always present, but is particularly intense during the charging phase of a new datum being output. In the charging phases each output buffer absorbs a relatively large current to charge the external load capacitance. This causes a noise spike that may slow down propagation of the signals inside the integrated circuit and/or cause errors.
An example of an integrated system are memory devices. Static memories are typical integrated systems that may be effected by switching noise caused by the array of data output buffers. The data output buffers may cause spurious switching of the input address latches. A read cycle in a nonvolatile memory is characterized by pointing to a new memory location, reading a new datum and outputting the new datum. In standard memory devices the reading of a new datum and the outputting of it takes place at different times. The effects of the noise spikes can thus be controlled in a relatively straightforward manner.
In contrast, in an interleaved memory the problem is more severe because each output buffer is slaved to distinct banks of the memory that alternately convey a new read datum. Through an internal common data bus, the control circuits of a bank transfer the new read datum towards the output circuits so the reading of a datum may take place at the same time the previously read datum (from a different bank) is being output. This makes the problems represented by the output switching noise more critical.
A similar situation may be present in any integrated digital system in which there are two or more asynchronous data sources that must be functionally conveyed, for example, in an interleaved manner. The data is provided to a single output register driving a single buffer (serial output stream), or an array of buffers (parallel output stream). The amplitude of the switching noise spikes can be reduced, according to a conventional technique, by limiting the maximum current absorbed by a buffer or an array of buffers while switching the output. This is done while slowing down the speed of the system.
When speed is of significant importance, there have been several proposals for reducing the switching noise by charging the output node to an intermediate voltage. The intermediate voltage is between the voltage corresponding to a high logic level of the output node and to the voltage of a low logic level of the output node. In this way, the actual switching of the output toward the logic level corresponding to the known datum to be output will occur under a reduced driving voltage. For the same speed, the current absorption from the supply rails can be reduced, and thus the amplitude of the noise spikes.
European Patent No. 251,910 discloses an output buffer wherein the switching noise is reduced by driving the gates of the driver through an appropriate RC circuit. A drawback of this approach is the reduced speed of the entire circuit. U.S. Pat. No. 5,179,300 discloses an output CMOS buffer with feedback loops to precharge the output node at an intermediate voltage between a logic high and a logic low. U.S. Pat. No. 4,893,276, U.S. Pat. No. 5,179,300 and U.S. Pat. No. 5,058,066 all disclose precharge circuits for a data output buffer. For memory devices, an input address transition detector circuit provides a useful pulse for commanding a precharging of the output node. This is done in expectation of a new datum to be output after being read from the memory cell array.
These known techniques, though effective in reducing output switching noise, have a number of shortcomings. There is a substantial unpredictability of the actual intermediate voltage level to which the output node is brought during the precharge phase.
The level of precharge of the output node forced by the circuitry stimulated from a command pulse remains uncorrelated from the actual state of charge of the output node. The command pulse is commonly derived from the input address transition detecting circuitry. For example, this is the case upon reentering from a stand-by period, or when the outputs are being forced by other devices of the system interfaced on the same data bus.
U.S. Pat. No. 5,058,066 discloses an output buffer precharge circuit for a DRAM wherein noise may be decreased during transitions from CMOS level to the TTL level by precharging the output node of the buffer. The precharging is done by using an auxiliary final stage timely driven for precharging the output node to an intermediate voltage level.
A drawback of these known approaches to the problem of reducing switching noise by precharging the output node to an intermediate voltage level is the fact that the precharge process is controlled only in terms of its evolution in time. This leaves to a large extent undetermined the actual precharging level that is directly tied to the actual capacitance of the driven external circuitry. This also includes the spread of electrical parameters in the fabrication process and/or in the conditions of operation (e.g., temperature). Another problem is that under certain circumstances undesirable oscillations of the output node from one logic state to another may be caused by the precharge loops.
SUMMARY OF THE INVENTION
An object of the present invention is to provide for the precharging of the output node of an output data buffer to a precisely established intermediate precharging voltage as a function of the preexisting state of charge of the output node.
This and other objects, advantages and features of the present invention are provided using an internal latch for storing the current logic state of the,output node of the buffer that controls the operation of the precharge circuit of the output node. Distinct reset signals are produced for the high side driver of the CMOS output stage P-channel transistor, and for the driver control logic of the N-channel transistor. These reset signals are obtained by comparing the signal present at the output of the internal latch with preestablished intermediate voltage threshold values.
The output buffer of the present invention has precharge loops for the output node that includes comparators that precisely set the intermediate voltage level of precharge, irrespective of external or incidental conditions. The precharging levels are preferrably defined in the design stage to exclude the possibility of causing oscillations about a single intermediate threshold level of precharging for the output node.
REFERENCES:
patent: 5058066 (1991-10-01), Yu
patent: 5638328 (1997-06-01), Cho
patent: 5796661 (1998-08-01), Kim
pat
De Ambroggi Luca Giuseppe
Nicosia Salvatore
Pagano Giovanni
Palumbo Gaetano
Allen Dyer Doppelt Milbrath & Gilchrist, P.A.
Galanthay Theodore E.
Nguyen Tan T.
STMicroelectronics S.r.l.
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