Data output buffer for a semiconductor memory

Details Data output buffer for a semiconductor memory Data output buffer for a semiconductor memory

1990-03-20

1992-11-03

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

365203, G11C 700

Patent

active

051611201

ABSTRACT:
A data output buffer is provided in connection with a semiconductor memory, such as a pseudostatic RAM, which is capable of high speed operation with respect to memory data readout. The buffer includes a latch circuit comprising a pair of NAND gate circuits having input and output terminals connected in cross connection, a pair of precharge MOSFETs provided respectively between the noninverted and inverted input terminals of the latch circuit, a pair of CMOS NAND gates which transfer the inverted signal of the latch circuit according to an inverted timing signal and a pair of series-connected MOSFETs effecting a pull-up/pull-down arrangement which receives the inverted signal of the output signal of the NAND gates.

REFERENCES:
patent: 4811295 (1989-03-01), Shinoda
Hitachi IC Memory Data Book, Hitachi, Ltd., pp. 229-234, Mar. 1987.

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