Data output buffer circuit of semiconductor memory device

Details Data output buffer circuit of semiconductor memory device Data output buffer circuit of semiconductor memory device

1995-12-29

1997-12-30

Yoo, Do Hyun

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

36518911, 327321, 326 62, G11C 1300

Patent

active

057038112

ABSTRACT:
A voltage detection unit between a data output buffer terminal and the gate a transistor which is used to dissipate a high level voltage on the internal data line. The detection unit thus prevents an undesired electrical path from existing in the data output buffer circuit. In one embodiment, the detection unit consists of an NMOS and PMOS transistor connected in series and having a shared node connected to the voltage dissipating transistor. In another embodiment, there is also connected an invertor between the shared node and the gates of the NMOS and PMOS transistors.

REFERENCES:
patent: 4678950 (1987-07-01), Mitake
patent: 5583815 (1996-12-01), Choi et al.

Affiliated with

Also associated with

Rating

Data output buffer circuit of semiconductor memory device does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Data output buffer circuit of semiconductor memory device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Data output buffer circuit of semiconductor memory device will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-209023