Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch
Patent
1996-04-29
1997-11-11
Zarabian, A.
Static information storage and retrieval
Read/write circuit
Having particular data buffer or latch
36518911, 326 57, G11C 1140
Patent
active
056871228
ABSTRACT:
For use in a semiconductor circuit device, a uniquely-arranged tri-state output buffer responds to a control signal generated in the semiconductor circuit device and a below-ground voltage level at an output terminal to prevent wasted drain current and substrate current, and reduce capacitance at the pull-up node driving the output terminal. The output buffer includes a power supply signal providing at least one voltage level with respect to common; an output terminal; a pull-up node; a pull-down node; a first circuit responding to the control signal by providing a first control voltage on the pull-up node; and a second circuit responding to the control signal by providing a second control voltage on the pull-down node. Further, the output buffer includes a pull-up transistor, responsive to the voltage on the pull-up node and coupled between the power supply signal and the output terminal; a pull-down transistor, responsive to the voltage on the pull-down node and coupled between common and the output terminal; a bias circuit, responsive to a voltage level on the output terminal being at a level substantially below common, arranged to bias the pull-up node downwardly and away from the voltage level provided by the power supply signal; and a disable circuit, responsive to the voltage level on the output terminal being at a level substantially below common, constructed and arranged to disable the circuit providing the control voltage on the pull-up node. The pull-up transistor provides a high-level signal at the output terminal, the pull-down transistor provides a low-level signal at the output terminal, and the bias circuit in combination with the disable circuit respond to the voltage level on the output terminal being at a level substantially below common by preventing current flow from the power supply signal to the output terminal.
REFERENCES:
patent: 4678950 (1987-07-01), Mitake
patent: 4772812 (1988-09-01), Desmaraias
patent: 4985644 (1991-01-01), Okihara
patent: 5281869 (1994-01-01), Lundberg
patent: 5311076 (1994-05-01), Park
Electronic News, "Samsung Pushes S-DRAMS to 1000 MHz", May 9, 1994, p. 52 (circuit depiction of Model KM44S4020AT attached).
Micro)n Technology, Inc.
Zarabian A.
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