Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch
Reexamination Certificate
2000-06-27
2001-09-11
Tran, Andrew Q. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Having particular data buffer or latch
C365S194000
Reexamination Certificate
active
06288947
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a DDR (Double Data Rate) synchronous DRAM; and, more particularly, to an apparatus and a method for controlling pipelatch input signals during a read operation in the DDR SDRAM.
DESCRIPTION OF THE PRIOR ARTS
As well-known to those skilled in the art to which the subject matter pertains, synchronous DRAMs, which are synchronized with external system clock signals, have been widely used to increase the speed thereof. Synchronous DRAMs (hereinafter, referred to as SDRAMS) are synchronized with a rising edge of the external system clock signal, but DDR SDRAMs are synchronized with both rising and falling edges of the external clock signal. Therefore, the DDR SDRAMs may increase operation speed twice as fast as SDRAMs without increasing frequency of the clock signals so that they are focused on the next generation DRAM devices. Furthermore, to process data continuously read out from memory cells, a plurality of pipeline latch circuits have been used in the SDRAMs.
FIG. 1
is a block diagram illustrating a data output path in a wave pipeline in which a plurality of pipelatch circuits to temporarily store cell data are arranged in parallel.
Referring to
FIG. 1
, four pipelatch circuits
30
to
33
are connected in parallel to global input/output lines gio<
0
> and /gio<
0
>. A data output unit
130
outputs data transferred through the global input/output lines gio<
0
> and /gio<
0
>, the pipelatch circuits
30
to
33
, and an output driver
131
in response to pipelatch control signals pcd (<
0
> to <
3
>) and pipe count signals pcnt (<
0
> to <
3
>). A pipelatch control signal generator
150
produces the pipelatch control signal pcd which selectively couples the pipelatch circuits
30
to
33
to the global input/output lines gio<
0
> and /gio<
0
>. Global input/output units
110
to
113
are provided between a cell array block and the data output unit
130
to transfer the cell data read out from the cell array block. A pipe count signal generator
170
, which produces the pipe count signal pcnt, selectively couples the pipelatch circuits
30
to
33
to the output driver
131
.
The data output unit
130
also includes first switching means
20
to
23
in order to selectively connect the global input/output lines gio<
0
> and /gio<
0
> to the pipelatch circuits
30
to
33
in response to the pipelatch control signals pcd and second switching means
40
to
43
in order to selectively connect the pipelatch circuits
30
to
33
to the output driver
131
in response to the pipe count signals pcnt.
The global input/output units
110
to
113
includes a plurality of input/output sense amplifiers (IOSAs) to transfer amplified data to the global input/output lines gio<
0
> and /gio<
0
> and a precharging unit to precharge the global input/output lines gio<
0
> and /gio<
0
> to a power supply voltage VCC. It should be noted that each of global input/output units
110
to
113
is coupled to the data output unit
130
even if only the global input/output unit
110
is coupled to the data output unit
130
in FIG.
1
.
FIG. 2
is a block diagram of the pipelatch control signal generator
150
in FIG.
1
. The pipelatch control signal generator
150
includes a pass gate control signal generator
330
, which produces a pass gate signal pcdinc by combining the global input/output lines signals gio<
0
:
3
> and /gio<
0
:
3
> and a pipelatch enable signal pcden, and a pipelatch selection signal generator
350
which produces the pipelatch control signals pcd<
0
>, pcd<
1
>, pcd<
2
> and pcd<
3
> to select one of the pipelatch circuits
30
to
33
in response to the pass gate signal pcdinc and the pipelatch enable signal pcden.
The pipelatch selection signal generator
350
includes a first circuit unit
360
and a second circuit unit
370
. The first circuit unit
360
includes first pass transistors P
10
, P
11
, P
12
and P
13
controlled by the pass gate signal pcdinc and second pass transistors P
20
, P
21
, P
22
and P
23
controlled by an inverted signal of the pass gate signal pcdinc. At nodes N
30
to N
33
, output signals of the first circuit unit
360
are produced by latch and buffer circuits which combine the pipelatch enable signal pcden and output signals from the second pass transistors P
20
, P
21
, P
22
and P
23
. The second circuit unit
370
outputs the pipelatch control signals pcd<
0
>, pcd<>, pcd<
2
> and pcd<
3
> using the output signals from the first circuit unit
360
and the pipelatch enable signal pcden.
FIGS. 3 and 4
are timing charts illustrating the wave pipeline having a plurality of pipelatch circuits and the pipelatch control signal generator in
FIGS. 1 and 2
, respectively. In a first read operation, one of the global input/output lines gio<
0
> and /gio<
0
>, which are precharged by the precharging unit, goes from a high voltage level to a low voltage level when the input/output sense amplifier (IOSA) in one of the global input/output units
110
to
113
is turned on and the data from the memory cell block are transferred thereto. At this time, the first switching means
20
is turned on by the pipelatch control signal pcd<
0
> from the pipelatch control signal generator
150
.
After the data are stored in the pipelatch circuit
30
for a predetermined time, a global input/output line precharge signal gio_precharge is activated in a low voltage level and the global input/output lines gio<
0
> and /gio<
0
> are precharged to a high voltage level. When the global input/output lines gio<
0
> and /gio<
0
> are precharged to a high voltage level, the pass gate signal pcdinc from the pass gate control signal generator
330
is in a high voltage level in response to the precharged global input/output lines gio<
0
> and /gio<
0
>, a signal at node N
30
is in a low voltage level, and then the first switching means
20
is disabled by the pipelatch control signal pcd<
0
> which is in a high voltage level in response to the signal at node N
30
and the pipelatch enable signal pcden.
On the other hand, a signal at node N
31
is in a high voltage level and the pipelatch control signal pcd<
1
> is in a low voltage level so that these signals makes the first switching means
21
enabled to form the data pass between the global input/output lines gio<
0
> and /gio<
0
> and the pipelatch circuit
31
. Since the pipelatch control signal pcd<
1
> is enabled when the pipelatch control signal pcd<
0
> is disabled, it should be noted that the data path between the global input/output lines gio<
0
> and /gio<
0
> and the pipelatch circuit
30
is turned on and the data path between the global input/output lines gio<
0
> and /gio<
0
> and the pipelatch circuit
31
is turned off simultaneously.
In like manner, one of the input/output sense amplifiers is selected in another read operation, the cell data are stored in the pipelatch circuit
31
through the above-mentioned procedures and the switching means
21
is disabled by the pipelatch control signal pcd<
1
> which is in a high voltage level. The third and fourth read operations are carried out by the pipelatch circuits
32
and
33
, respectively. The data stored in the pipelatch circuits
30
to
33
are output through the output driver
131
in response to the pipe count signals pcnt<
0
:
3
>.
However, the above-mentioned read operation using the pipelatch circuits has some drawbacks because the distance between the input/output sense amplifier IOSA and the pipelatch circuits
30
to
33
is not constant. That is, since the data transferred by the input/output sense amplifier IOSA, which is far away from the pipelatch circuit, has a low transmission rate and a narrow bandwidth, the data skew may occur based on the position of the input/output sense amplifiers IOSAs. This skew may
Jeong Dong-Sik
Kim Kwan-Weon
Hyundai Electronics Industries Co,. Ltd.
Jacobson & Holman PLLC
Tran Andrew Q.
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