Data output apparatus for memory device

Details Data output apparatus for memory device Data output apparatus for memory device

2006-04-18

2006-04-18

Zarabian, Amir (Department: 2827)

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

C365S189011, C365S189110

Reexamination Certificate

active

07031200

ABSTRACT:
A data output circuit for a memory device improves data transfer speed from the memory device by re-amplifying stored data using by a bitline sense amplifier and transferring it to global input/output lines. Data read from the memory device is coupled to an amplifier interposed between the first and second “local” data lines. CMOS buffers receive data on first and second local data lines and outputs the data to first and second latches, the outputs of which are coupled to the inputs of a series connected pull-up transistor and a pull-down transistor coupled between a driving voltage and a ground terminal in series.

REFERENCES:
patent: 6741521 (2004-05-01), Kono
patent: 2004/0189352 (2004-09-01), Jeon

Affiliated with

Also associated with

Rating

Data output apparatus for memory device does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Data output apparatus for memory device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Data output apparatus for memory device will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3622516