Data out buffer circuit and SRAM

Details Data out buffer circuit and SRAM Data out buffer circuit and SRAM

1999-06-18

2000-09-19

Phan, Trong

Static information storage and retrieval

Read/write circuit

Precharge

36518905, 36523008, G11C 700, G11C 1604, G11C 800

Patent

active

061222100

ABSTRACT:
It is an object of the invention to ensure a signal transmission time of a data out buffer circuit of a SRAM which adopts a pre-charge system. The data out buffer circuit is provided with a pre-charge circuit for pre-charging a write/read bus during a period of pre-charge and a data latch circuit for holding a data read before then during the period of pre-charge. The data out buffer circuit outputs the data held in the data latch circuit during the period of pre-charge to the outside via a data output circuit. The reliability of the data transmission achieved by the extended holding time of the output data and the improvement of access speed achieved by pre-charge can be both realized.

REFERENCES:
patent: 5311471 (1994-05-01), Matsumoto et al.
patent: 5408437 (1995-04-01), Cho et al.
patent: 5583456 (1996-12-01), Kimura
patent: 5654927 (1997-08-01), Lee
patent: 5694369 (1997-12-01), Abe
patent: 5886936 (1999-03-01), Yang

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