Static information storage and retrieval – Read/write circuit – Precharge
Reexamination Certificate
2001-11-02
2004-05-25
Phan, Trong (Department: 2818)
Static information storage and retrieval
Read/write circuit
Precharge
C365S230060, C365S158000
Reexamination Certificate
active
06741513
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The invention lies in the memory technology field and pertains, more specifically, to data memory with a plurality of banks. Each of the plurality of banks contains a multiplicity of memory cells which form a matrix-shaped array of rows and columns with respectively assigned row lines and column lines. The row lines of each bank can be activated selectively, and the column lines of each bank are connected to a column-driving device which is assigned to the respective bank and which contains, for each column line, a column selection switch that can be switched on selectively and which, in the switched-on state, transmits, from or to an associated column-connecting node of a data line network, the data value which is to be written on the respective column line or read out.
Data memories which are constructed using solid state technology and are designed for random access (generally referred to as RAMs) usually contain a plurality of “banks” each composed of a multiplicity of memory cells, each bank forming a matrix-shaped arrangement of rows and columns with respectively assigned matrix row lines and column lines. The matrix row lines of each bank are connected to a group of matrix row line drivers which are assigned to the respective bank. The column lines of each bank are connected to a column-driving device which is assigned to the respective bank and which contains, inter alia, a column-selection switch which can be switched on selectively for each column line. It is thus possible to address each memory cell of a bank in a uniquely defined fashion by driving a specific matrix row line and switching on a specific column-selection switch.
In order to write an item of information into a desired memory cell or read an item of information from it, the matrix row line which is assigned to the matrix row containing the respective cell is activated by a specific level being applied by a matrix row address decoder, as a result of which all the cells of this matrix row are prepared for possible access (matrix row addressing). The actual access is then made by that column-selection switch which is assigned to the column containing the desired memory cell and is switched on by a column-address decoder (column addressing). For the purpose of writing, a data value, i.e. a current level or voltage level which represents the information to be written is applied to the respective column line. For the purpose of reading, the data value which is stored in the selected cell and is connected to the respective column line from this memory cell on the basis of the activated matrix row line is sensed at this column line by means of a sense amplifier.
The memory cells of currently customary dynamic RAMs (generally referred to as DRAMs) store the information capacitively, i.e., in the form of electrical charge which has to be refreshed at short time intervals owing to its highly volatile nature and which is additionally used up during reading. In order to restore the memory state, damaged in this way, of such a cell after the reading operation, the sensed data value is buffered (“latched”) in the column amplifier in order to, on the one hand, write it back from there into the respective cell and, on the other hand, transmit it to a common bidirectional data port of the memory via a data line network. When a matrix row line has been activated, the data values of all the memory cells of the respective matrix row are usually simultaneously sensed and latched by the column amplifier and the latched data values are then successively transmitted via the data line network to the data port of the memory. This operation and the continuously necessary refreshing of the memory contents requires a separate sense amplifier for each column, at the end of the respective column line. The sequential transmission of the data values between the individual sense amplifiers and the data line network is carried out by means of corresponding sequential driving of the column-selection switches.
As a result of the splitting up of the overall quantity of memory cells of a RAM memory into a plurality of banks which can be operated independently of one another, the data rate can be increased. If each data bank has its own row- and column-driving means, the banks can be operated virtually in parallel with one another in order to conceal the unavoidable delays which result from the development period of the signals. In the case of banks which can be operated independently, it is possible, for example, for a column access to a bank to be already started while another bank is still in the stage of the signal development for the reading operation. In this way, data values which are to be written to various memory cells or read out from them can be transmitted to or from the data port of the memory via the data line network at much shorter time intervals.
The problem with such a multi-bank architecture of a memory is posed by differences in signal transit times owing to signal paths of different lengths between the column-driving devices of various banks and the common data port. If more than two banks are present, it is unavoidable that cases will occur wherein the distances from the data port to two different column-connecting points of the data line network will deviate from one another by more than the dimension of one column length (length of a bank) or of one matrix row length (width of a bank), which can lead to differences in signal transit times of several nanoseconds. Given the previous multi-bank memories, it is therefore necessary to adjust the exact timing of driving signals within a correspondingly wide framework. This is often achieved with self-timing signals, i.e. the system waits until a data signal has reached its final state at the point which is farthest away from the data port, and only then does it begin to process the rest of the signal sequence. In other, more general terms: in order to take into account the aforethe differences in signal transit times there must be a corresponding degree of room for maneuver in the cycles of the clock with which the data values are clocked over the common data line. This restricts the maximum possible data rate. In addition, the speed of a changeover between writing mode and reading mode is restricted by the absolute signal transit time between the data port and the column-connecting point of the data line network which is furthest away.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a data memory device with a plurality of memory banks, which overcomes the above-mentioned disadvantages of the heretofore-known devices and methods of this general type and wherein the differences in the line lengths between the common data port and the various column-connecting points of the data line network are smaller than hitherto and wherein the line length between the data port and the column-connecting point lying farthest away is smaller than hitherto.
With the foregoing and other objects in view there is provided, in accordance with the invention, a data memory device, comprising:
a plurality of memory banks each containing a multiplicity of memory cells arranged in a matrix array of rows and columns and having respectively assigned matrix row lines and column lines, whereby the matrix row lines of each memory bank are selectively activatable;
column-driving devices connected to ends of the column lines and each assigned to a respective bank, the column-driving devices having, for each column line, a selectively switchable column selection switch connected to transmit, in a switched-on state thereof, from or to an associated column-connecting node of a data line network, a data value to be written on or read out from the respective column line;
the banks being spatially arranged on top of one another to form bank stacks with edges extending parallel to the matrix rows and having the ends of the column lines connected to the column-driving devices, the edges lying in a common plane extending in the di
Hönigschmid Heinz
Möller Gerhard
Greenberg Laurence A.
Infineon - Technologies AG
Locher Ralph E.
Phan Trong
Stemer Werner H.
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