Data inversion register technique for integrated circuit...

Details Data inversion register technique for integrated circuit... Data inversion register technique for integrated circuit...

2007-10-07

2009-12-08

Tu, Christine T (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

C714S823000

Reexamination Certificate

active

07631233

ABSTRACT:
A data inversion register technique for integrated circuit memory testing in which data input signals are selectively inverted in a predetermined pattern to maximize the probability of identifying failures during testing. In accordance with the technique of the present invention, on predetermined input/outputs (I/Os,) data inputs may be inverted to create a desired test pattern (such as data stripes) which are “worst case” for I/O circuitry or column stripes which are “worst case” for memory arrays. A circuit in accordance with the technique of the present invention then matches the pattern for the data out path, inverting the appropriate data outputs to obtain the expected tester data. In this way, the test mode is transparent to any memory tester.

REFERENCES:
patent: 5940874 (1999-08-01), Fulcomer
patent: 6769081 (2004-07-01), Parulkar
patent: 6918075 (2005-07-01), Matsui
patent: 7302622 (2007-11-01), Beer

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