Data interface methods and circuitry with reduced latency

Details Data interface methods and circuitry with reduced latency Data interface methods and circuitry with reduced latency

2011-07-19

2011-07-19

Tsai, Henry W (Department: 2184)

Electrical computers and digital data processing systems: input/

Input/output data processing

Input/output data buffering

C710S054000, C710S058000, C711S001000, C711S167000, C375S372000

Reexamination Certificate

active

07984209

ABSTRACT:
Interface circuitry that is used to interface data between two different clock regimes that may have somewhat different speeds includes the ability to determine which of the clock regimes is faster. Depending on which clock regime is found to be faster, the baseline (nominal difference between data write and data read addresses of a FIFO memory in the interface circuitry) is shifted (i.e., toward the full or empty condition of the FIFO, as is appropriate for which of the clock regimes has been found to be faster). Adjustments may also be made to the threshold(s) used for such purposes as character insertion/deletion and overflow/underflow indication. This technique may allow use of a smaller FIFO and reduce latency of the interface circuitry.

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