Data integrity verifying circuit for electrically erasable and p

Details Data integrity verifying circuit for electrically erasable and p Data integrity verifying circuit for electrically erasable and p

1986-06-20

1989-03-07

Hecker, Stuart N.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

365201, 365185, 365218, 371 21, G11B 700, G11B 1140

Patent

active

048112941

ABSTRACT:
An EEPROM provided with a write/erase checking circuit comprising, a data detector for determining whether one byte in an input data contains a "0" (representing that a memory cell is not in an erase state); an address latch circuit and a data latch circuit which latch the address and the input data, respectively, responsive to a detection signal from the data detector; a data read circuit which selects the memory cells according to the address stored in the address latch circuit and reads the data out of the memory cells at the data write checking; and a comparator which compares the data from the data read circuit with the data stored in the data latch circuit.

REFERENCES:
patent: 4460982 (1984-07-01), Gee et al.
patent: 4578751 (1986-03-01), Erwin
patent: 4675513 (1987-06-01), Kuze
"An Enhanced 16K E.sup.2 PROM", L. Gee et al., IEEE Journal of Solid-State Circuits, vol. SC-17, No. 5, Oct. 1982.

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