Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch
Reexamination Certificate
2002-03-15
2003-11-18
Le, Vu A. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Having particular data buffer or latch
C365S233100, C711S167000
Reexamination Certificate
active
06650573
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for data input/output for a memory. More particularly, the present invention relates to a method for data input/output for a memory that minimizes data interruption when switching between reading and writing.
2. Background of the Invention
DRAM has been a bottleneck for improving the performance of computers since the speed of DRAM is slower than the microprocessor unit (MPU). Therefore, various kinds of fast schemes, such as a burst mode of SDRAM (Synchronous Dynamic RAM) and RAMBUS, are utilized. These are all based on the page mode where data are retrieved from the conventional sense amplifiers that latches the data. A large number of sense amplifiers are activated such that data to be accessed could possibly be at the addresses of the sense amplifiers that have already been activated. Furthermore, a number of banks may be provided to make the number of data latched in the sense amplifiers large, or another bank may be accessed when an access is made to an address that does not exist in the sense amplifiers latched in a bank, in order to achieve an increase in speed.
BRIEF SUMMARY OF THE INVENTION
Under practical use conditions of a semiconductor memory where data is stored and retrieved, such as DRAM, an access to memory is essentially random row access where any row address (word line) is accessed. Though these memories are practically used in the random row access mode, these memories tend to avoid this access as much as possible and rely on the page mode or banks for increasing speed. As a result, when accesses occur in the same bank, data are interrupted between the bursts. Particularly, it has a significant affect when reading and writing are switched one after the other.
FIG. 5
depicts an example for SDRAM DDR (Double Data Rate).
FIG. 5
shows the case where reading from and writing to addresses in the same bank occur alternately under the conditions where CAS (Column Address Strobe) latency is two and the burst length is eight. It is evident from the drawing that there are long empty periods between the bursts in terms of data I/O. There are 18 clocks for one cycle of reading and writing, during which 8 bursts of reading and 8 bursts of writing are performed on both edges of the clock. Therefore, among 36 clock edges, only 16 clock edges are involved in the processing of data. Namely, the data rate in this case is only 44% (=16/36) compared with the peak data rate where all edges are used. This means that even if the clock frequency is 200 MHz, an actual data rate is equivalent to 88 MHz. In this manner, in the practical random row access environment where reading and writing are frequently switched, there are drawbacks where the data rate can not be increased.
In order to cope with the problems associated with the random row access, a row-to-row seamless access will be described. A memory array is essentially composed of a matrix where word lines and bit lines are orthogonalized, wherein subsequent another address can not be accessed while either of which is operated. The period from onset of word line rising completion of bit line equalization is called the array time constant. In other words, the cycle time of memory can be reduced to this array time constant in theory. Based on this, row-to-row seamless access could become possible by greatly reducing the array time constant utilizing prefetch and preload to make it shorter than the time required for the burst.
FIG. 6
depicts an operation provided that the same reading and writing as that in
FIG. 5
occurs alternately. In this case, the page mode is eliminated, wherein precharge occurs right after all the accesses have prefetched data or right after preloaded data has been written at a time, thus a command need not be divided into RAS (Row Address Strobe) and CAS (Column Address Strobe), whereby one command identified of its reading or writing is provided to a row and column addresses at the same time.
In
FIG. 6
, since the array time constant is reduced compared with
FIG. 5
, the empty period of time where no data exists is greatly reduced in the data I/O. There exists one clock of empty period between the bursts. This empty period is provided intentionally to avoid data contention on the bus between the memory and the driver of the controller chip. If both the chips use a driver of the type of open drain being pulled-up externally, this one clock of empty period is unnecessary, whereby all the bursts result in a seamless data stream. Therefore, in this case, an access is considered to be made at the peak data rate.
However, actual reading and writing may occur in any pattern rather than such a simple repetitive pattern. As shown in
FIG. 7
, for example, where reading occurs two times consecutively and writing occurs one time, data are processed using 24 clock edges among 42 clock edges, consequently the data rate is 57% (=24/42). This is better than the data rate of 44% in
FIG. 5
, but still considered to be low. Since the above-mentioned method uses separate buses between reading and writing, the reading and writing could be made at the same timing on the buses, whereby the array time constant for the writing could be placed right after the array time constant for the second reading. However, when a common I/O is used, it is difficult to increase the data rate.
It is therefore an object of the present invention to provide a method for data input/output for a memory which minimizes losses of data interruption when switching between reading and writing.
In one aspect of the present invention, there is provided a method for data input/output for DRAM that uses common I/O to read and write data, the method comprises the steps of: holding predetermined data from a memory array upon m-th (m is integer) read command; outputting the predetermined data to the common I/O and holding new data from the memory array upon (m+1)-th read command; holding predetermined data from the common I/O upon n-th (n is integer) write command; and storing the predetermined data in the memory array and holding new data from the common I/O upon (n+1)-th write command.
In another aspect of the present invention, there is provided a DRAM comprising a prefetch/latch circuit for holding data from a memory array and a preload/latch circuit for holding data from common I/O, wherein the prefetch/latch circuit comprises: means for holding predetermined data from the memory array upon m-th (m is integer) read command; means for outputting the predetermined data to the common I/O upon (m+1)-th read command; and means for holding new data from the memory array upon (m+1)-th read command; and wherein the preload/latch circuit comprises: means for holding predetermined data from the common I/O upon n-th (n is integer) write command; means for storing the predetermined data in the memory array upon (n+1)-th write command; and means for holding new data from the common I/O upon (n+1)-th write command.
REFERENCES:
patent: 5835446 (1998-11-01), Park
patent: 5923595 (1999-07-01), Kim
patent: 6081479 (2000-06-01), Ji et al.
Sunaga Toshio
Watanabe Shinpei
Canale Anthony J.
Hur Jung H.
Le Vu A.
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