Data input/output managing device, particularly for a non-volati

Details Data input/output managing device, particularly for a non-volati Data input/output managing device, particularly for a non-volati

1997-03-07

1998-09-29

Nelms, David C.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

36518509, 36518905, 365200, G11C 1134, G11C 700

Patent

active

058154370

ABSTRACT:
A data input/output managing device, particularly for non-volatile memories that comprise at least one matrix of memory cells. The managing device comprises: at least one bidirectional internal bus for the transfer of data from and to the memory; a redundancy management line that is associated with the internal bus; means for enabling/disabling the transmission, over the internal bus, of the data from the memory toward the outside; means for enabling/disabling access to the internal bus on the part of data whose source is other than the memory matrix, for transmission to the memory matrix; and means for enabling/disabling the connection between the outside of the memory and the redundancy line during the reading of the memory matrix and during its programming.

REFERENCES:
patent: 4426688 (1984-01-01), Moxley
European Search Report fron European Patent Application 98603127.5, filed Mar. 20, 1996.
IEEE Journal of Solid-State Circuits, vol. 27, No. 11, Nov. 1, 1992, pp. 1525-1531, Akira Tanabe, et al., "A 30-NS 64-MB Dram With Built-In Self-Test and Self-Repair Function".

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