Data input device of a DDR SDRAM

Details Data input device of a DDR SDRAM Data input device of a DDR SDRAM

2005-02-01

2005-02-01

Elms, Richard (Department: 2824)

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

C365S193000, C365S233100, C365S189020

Reexamination Certificate

active

06850444

ABSTRACT:
A data input device of a DDR SDRAM includes at least a clock pulse generator (for outputting a data-in-strobe signal based on internal clock), first and second data buffers (being controlled by the data-in-strobe signal and having output lines corresponding to first and second global input-output lines, respectively). When a second control signal is low, the first data is directly applied to the first data buffer for transfer to the first global input/output line, and the second data is directly applied to the second data buffer for transfer to the second global input/output line. When the second control signal is high, the first data is directly applied to the second data buffer for transfer to the second global input/output line, and the second data is directly applied to the first data buffer for transfer to the first global input/output line. The time for the write operation is reduced by directly applying the write-in-strobe signal to the data buffers.

REFERENCES:
patent: 6512719 (2003-01-01), Fujisawa et al.
patent: 6639868 (2003-10-01), Kim et al.
patent: 6671211 (2003-12-01), Borkenhagen et al.

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