Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch
Reexamination Certificate
2002-10-23
2004-03-16
Elms, Richard (Department: 2824)
Static information storage and retrieval
Read/write circuit
Having particular data buffer or latch
C365S193000, C365S233100
Reexamination Certificate
active
06707723
ABSTRACT:
This application claims priority and benefit of Korean Patent Application No. 2001-68840, filed on Nov. 6, 2001, the contents of which are incorporated herein by reference in their entirety.
BACKGROUND
The present invention relates to a synchronous semiconductor memory device, and more particularly, to a data input circuit and method of inputting data to a synchronous semiconductor memory device.
A semiconductor memory device may be used as a main memory in a computer system for input and output of data into and from memory cells of the memory device. The data input/output speed of a semiconductor memory device may be very important in deciding an operating speed of a computer system. As a result, there have been continual efforts to improve the operating speeds of semiconductor memory device.
As a result of these efforts, a synchronous dynamic random access memory (SDRAM) has evolved to include internal circuits that control memory operations in synchronization with a clock signal of, e.g., a computer system. Examples of SDRAM may include a single data rate SDRAM (SDR SDRAM) and a double data rate SDRAM (DDR SDRAM). The SDR SDRAM may input or output one data per cycle of a clock signal responsive to a rising or falling edge of the clock signal. On the other hand, the DDR SDRAM may input or output two data per cycle of a clock signal to a first rising edge and then a falling edge of the clock signal. That is, the bandwidth of the DDR SDRAM may be twice that of the SDR DRAM.
With twice the transfer rate, the DDR SDRAM may be understood to have a window of opportunity for transfer of data to/from the DDR SDRAM that is smaller than that of the SDR SDRAM. To accommodate the smaller windows, a data strobe signal may be used to assist controlled retrieval of data from an input/output data signal. Thus, the DDR SDRAM may include an extra pin to allow input of the data strobe signal.
FIG. 1
is a block diagram of a data input circuit for a conventional synchronous semiconductor memory device. Referring to
FIG. 1
, data input circuit
100
includes data input buffer
110
, data delay circuit
112
, data fetch circuit
120
, synchronous circuit
140
, data strobe buffer
160
, first delay circuit
162
, a second delay circuit
164
, clock input buffer
180
, and auto pulse generation circuit
182
. An external input data signal DIN, an external data strobe signal DS, and an external clock signal CLK may be applied to inputs of data input buffer
110
, data strobe buffer
160
, and clock input buffer
180
, respectively.
During operation of data input circuit
100
, data may be fetched from an internal data signal PDIND responsive to data strobe signal PDSD
1
. The fetched signal may then be converted into two separate internal parallel data signals DI_F and DI_S. Data may then be fetched from the internal parallel data signals DI_F and DI_S in response to the data strobe signal PDSD
2
further delayed and may then be synchronized with an internal clock signal PCLK
2
to provide parallel data signals DIN_F and DIN_S.
A phase difference between the external data strobe signal DS and the external clock signal CLK may cause variations of up to a half cycle between the two. A technical standard tDQSS may indicate a timing margin between the external clock signal CLK and the external data strobe signal DS, which may include two different cases: CASE
1
and CASE
2
. In a first case, the technical standard tDQSS may be 0.75 tCK (hereinafter, referred to as tDQSS_MIN) and the phase of the external data strobe signal DS may lead that of the external clock signal CLK by tCK/
4
. In a second case, the technical standard tDQSS may be 1.25 tCK (hereinafter, referred to as tDQSS_MAX) and the phase of the external data strobe signal DS may lag that of the external clock signal CLK by tCK/
4
. Here, tCK represents a duration of one period or one cycle of the external clock signal CLK.
FIG. 2
is a timing diagram useful for describing exemplary operations of the data input circuit of
FIG. 1
for examples where the cycle of the external clock signal CLK may be relatively large. Referring to
FIG. 2
, the first case of operation (CASE
1
) shows operation of data input circuit
100
where the technical phase standard is tDQSS_MIN. The second case of operation (CASE
2
) shows operation of the data input circuit
100
where the technical standard is tDQSS_MAX. Further referencing
FIG. 2
, a data set-up time tDS may reference a duration required for set-up of data and a data hold time tDH a duration required for data of an external input data signal DIN to be presented or held at an input relative to a rising edge of the data strobe signal DS. Internal parallel data signals DII_F and DII_S represent internal data signals from which the internal parallel data signals DI_F and DI_S may be fetched by the second internal data strobe signal PDSD
2
.
In the first case, CASE
1
of tDQSS_MIN, the phase of the external data strobe signal DS leads that of the external clock signal CLK by tCK/
4
. In order to synchronize the external input data signal DIN as fetched by the external data strobe signal DS with the phase of the external clock signal CLK, it may be understood that a seemingly large delay may be required between the edge of the internal data strobe signal PDSD
1
and that of the internal data strobe signal PDSD
2
. This delay time T
1
as shown in
FIG. 2
should be large enough in order to allow retrieval of valid data from the respective data signal.
In the second case CASE
2
of tDQSS_MAX, the phase of the external data strobe signal DS may lag that of the external clock signal CLK by tCK/
4
. In order to synchronize the external input data signal DIN fetched by the external data strobe signal DS with the external clock signal CLK, a small delay may be needed between edges of the internal data strobe signal PDSD
1
and the internal data strobe signal PDSD
2
to allow retrieval of valid data from the data signal. This delay time T
2
as shown in
FIG. 2
might need to be less than that of the first case.
However, the conventional data input circuit
100
may use a fixed delay for the establishment of the second internal data strobe signal PDSD
2
relative the first PDSD
1
. As a result, the operating characteristics for the above-mentioned cases of tDQSS_MIN and tDQSS_MAX may remain fixed and may compromise synchronization at the two different extremes. That is, since the delay duration that is used for establishing the second internal data strobe signal PDSD
2
from the first PDSD
1
may be fixed, regardless of a cycle length or frequency of the clock signal, the timing margin due to this fixed delay duration may become insufficient when the cycle length of the external clock signal CLK decreases as the operating frequency increases.
FIG. 3
is a timing diagram useful for describing an operation of the conventional data input circuit of
FIG. 1
when the cycle of the external clock signal CLK may be relatively small. It may be observed from the exemplary depictions of
FIG. 3
that synchronization data failures may result during the short cycle clock operations of the conventional data input circuit
100
.
For example, for the case of tDQSS_MIN (CASE
1
), variations in process, voltage, and/or temperature may cause the duration T
1
for the delay associated with generating the second internal data strobe signal PDSD
2
from the first PDSD
1
to decrease. Under certain conditions, such reductions may interfere with the effective generation of internal parallel data signals DIN
0
and DIN
1
in the CASE
1
conditions.
In another example for the case of tDQSS_MAX (CASE
2
), variations in process, voltage, and/or temperature may cause the duration T
2
associated with the delay for generating of the second internal data strobe signal PDSD
2
from the first PDSD
1
to increase. Such increases might then cause generation of invalid data under the CASE
2
conditions.
SUMMARY OF THE INVENTION
Addressing some of the above problems, embodiments of the present invention may provide a data input circuit and associ
Elms Richard
Marger & Johnson & McCollom, P.C.
Nguyen Nam
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