Data input circuit of semiconductor memory apparatus and...

Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch

Reexamination Certificate

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Details

C365S191000, C365S194000, C365S233130, C365S233180

Reexamination Certificate

active

07742345

ABSTRACT:
A data input circuit for a semiconductor memory apparatus includes a write latency control unit configured to generate a buffer enable signal based on a low frequency operation mode signal, and a data input buffer configured to buffer input data in response to the buffer enable signal.

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