Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch
Reexamination Certificate
2007-07-02
2010-06-22
Nguyen, Tuan T (Department: 2824)
Static information storage and retrieval
Read/write circuit
Having particular data buffer or latch
C365S191000, C365S194000, C365S233130, C365S233180
Reexamination Certificate
active
07742345
ABSTRACT:
A data input circuit for a semiconductor memory apparatus includes a write latency control unit configured to generate a buffer enable signal based on a low frequency operation mode signal, and a data input buffer configured to buffer input data in response to the buffer enable signal.
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Hynix / Semiconductor Inc.
Kaminski Jeffri A.
Nguyen Tuan T
Reidlinger R Lance
Venable LLP
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