Data holding circuit and buffer circuit

Details Data holding circuit and buffer circuit Data holding circuit and buffer circuit

1997-10-14

1999-01-12

Nguyen, Tan T.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

36518908, G11C 700

Patent

active

058598006

ABSTRACT:
A highly reliable data holding circuit with a reduced circuit area and reduced power consumption is disclosed. Output terminals (DO, DOB) are connected to input terminals (DI, DIB) receiving signals at H and L levels (potentials VDD and GND) in mutually exclusive relation through transistors (MN2, MN1) and inverters (INV1, INV2). Input terminals of the inverters (INV1, INV2) are connected to power supplies (VDD) through transistors (MP2, MP1) having gate electrodes connected to output terminals of the inverters (INV2, INV1), respectively. The transistors (MN2, MN1) cause a voltage drop of the signals to be applied to the inverters (INV1, INV2) by the amount of a threshold voltage (Vthn). One of the transistors (MP1, MP2) which receives a signal at L level at its control terminal provides a potential (VDD) to the input terminal of one of the inverters (INV1, INV2) which is to output a signal at L level, compensating for the voltage drop by the amount of the threshold voltage (Vthn).

REFERENCES:
patent: 5384735 (1995-01-01), Park et al.
patent: 5406528 (1995-04-01), Kim
patent: 5424983 (1995-06-01), Wojcicki et al.
patent: 5561634 (1996-10-01), Yang

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