Data decoding apparatus and method in a communication system

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction

Reexamination Certificate

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Details

C714S760000, C714S791000, C714S797000, C702S009000, C326S011000

Reexamination Certificate

active

07962841

ABSTRACT:
A majority voting Viterbi decoder includes a branch metric calculator (BMC) for measuring a difference between a received symbol and a reference symbol and outputting branch metrics from the difference; an add-compare-selection (ACS) unit for determining an optimal path using the branch metrics; a survival path memory unit for outputting decoded symbols by performing decoding based on the optimal path; and a majority voting unit for determining a final decoded symbol by performing majority voting for the decoded symbols output from the survival path memory unit. Accordingly, by adding the majority voting unit, a decoding depth can be reduced without the loss of an encoding gain required in a system, and by reducing the decoding depth, miniaturization is possible, power consumption can be reduced, and a processing delay in a memory can be minimized.

REFERENCES:
patent: 4715037 (1987-12-01), Yagi
patent: 6473477 (2002-10-01), Watanabe
patent: 6877132 (2005-04-01), De et al.
patent: 7187729 (2007-03-01), Nagano
patent: 2002/0174402 (2002-11-01), Yamamoto

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