Data bus arrangement and control method for efficiently...

Details Data bus arrangement and control method for efficiently... Data bus arrangement and control method for efficiently...

2006-07-04

2006-07-04

Baderman, Scott (Department: 2114)

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

C710S305000

Reexamination Certificate

active

07073088

ABSTRACT:
The present invention discloses a data bus connecting individual modules and carrying data there between. The data bus includes primary signal lines and supplementary signal lines. A master module having a bus monitor and a microprocessor detects for faulty signal lines and substitutes supplementary signal lines for faulty primary signal lines enabling the bus to continue carrying data between modules connected thereto. The status of the signal lines are communicated to all the other modules on the bus by a special signal line on the bus so that each module is informed of the substitution.

REFERENCES:
patent: 5666480 (1997-09-01), Leung et al.
patent: 5864656 (1999-01-01), Park
patent: 5905875 (1999-05-01), Takahashi et al.
patent: 6034995 (2000-03-01), Eisele et al.
patent: 6182248 (2001-01-01), Armstrong et al.
patent: 6298376 (2001-10-01), Rosner et al.
patent: 6311296 (2001-10-01), Congdon
patent: 6345332 (2002-02-01), Okazaki
patent: 6349370 (2002-02-01), Imamura
patent: 6434703 (2002-08-01), Parrish et al.
patent: 6449729 (2002-09-01), Sanders et al.
patent: 6633996 (2003-10-01), Suffin et al.
patent: 6871294 (2005-03-01), Phelps et al.
patent: 2002/0099980 (2002-07-01), Olarig
patent: 2004/0136319 (2004-07-01), Becker et al.
patent: 2004/0260983 (2004-12-01), Leung et al.
patent: 2000 222294 (2000-08-01), None
patent: WO 98-44417 (1998-10-01), None
Partial English language translation of JP2000-222294 (accompanied by the Certificate of Translation).
Computerized English language translation of JP2000-222294 (abstract, claims and detailed description), available at Japanese Patent Office website.

Affiliated with

Also associated with

Rating

Data bus arrangement and control method for efficiently... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Data bus arrangement and control method for efficiently..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Data bus arrangement and control method for efficiently... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3599637