Data bus architecture for a semiconductor memory

Details Data bus architecture for a semiconductor memory Data bus architecture for a semiconductor memory

2007-08-21

2007-08-21

Lam, David (Department: 2827)

Static information storage and retrieval

Read/write circuit

Precharge

C365S207000, C365S205000

Reexamination Certificate

active

11281932

ABSTRACT:
A semiconductor memory device is provided that includes memory cells, sense amplifiers, signal lines, isolating circuits, and a precharging circuit. Each signal line is coupled to an output of at least one of the sense amplifiers and each of the isolating circuits isolates an associated signal line from the output of the corresponding sense amplifier at least during an evaluating phase of the datum stored in the memory cell. The signal lines include at least two groups of signal lines, arranged such that coupling capacitances between the lines of the first group and the lines of the second group are substantially negligible. The precharging circuit precharges the first group of signal lines to a first voltage level and the second group of signal lines to a second voltage level.

REFERENCES:
patent: 6351150 (2002-02-01), Krishnamurthy et al.
patent: 6442069 (2002-08-01), Srinivasan et al.
patent: 6442089 (2002-08-01), Fletcher et al.
patent: 6480434 (2002-11-01), Lee

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