Data buffer circuit with delay circuit to increase the length of

Details Data buffer circuit with delay circuit to increase the length of Data buffer circuit with delay circuit to increase the length of

1992-06-15

1994-05-24

Westin, Edward P.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307451, 307263, H03K 512, H03K 190948

Patent

active

053151739

ABSTRACT:
A data output buffer includes a data driving circuit having a pull-up transistor responsive to a first signal and a pull-down transistor responsive to a second signal, a first control circuit for regulating the slope of the first signal to be less steep after reaching the threshold of the pull-up transistor than before reaching the threshold of the pull-up transistor, and a second control circuit for regulating the slope of the second signal to be less steep after reaching the threshold of the pull-down transistor than before reaching the threshold of the pull-down transistor. As a result, noise generated by the transition of the output signal of the data output buffer is reduced without affecting operation speed.

REFERENCES:
patent: 4612466 (1986-09-01), Stewart
patent: 4825101 (1989-04-01), Walters, Jr.
patent: 4827159 (1989-05-01), Naganuma
patent: 4859870 (1989-08-01), Wong et al.
patent: 4877980 (1989-10-01), Kubinec
patent: 4880997 (1989-11-01), Steele
patent: 5175445 (1992-12-01), Kinugasa et al.

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