Fishing – trapping – and vermin destroying
Patent
1990-12-27
1993-05-04
Fourson, George
Fishing, trapping, and vermin destroying
437 43, 437 67, H01L 2176, H01L 2170, H01L 214763
Patent
active
052081796
ABSTRACT:
A method of fabricating a semiconductor integrated circuit comprises the steps of selectively forming a first gate insulating film on a main surface of a semiconductor substrate. Thereafter, the following layers are formed in sequence on the substrate: a first polysilicon layer, a second gate insulating film, and a second polysilicon layer. Then, insulating trenches are formed by selectively removing the second polysilicon layer, the second gate insulating film, the first polysilicon layer, the first gate insulating film, and the semiconductor substrate. Thereafter, a BPSG film is formed over the entire surface, filling the trenches. Selectively removing the BPSG film to leave it only in the trenches. Heretofore, the phosphorus and boron contained in the BPSG evaporated in response to a heat treatment used for forming the gate SiO.sub.2 film. Therefore, a portion of the evaporated phosphorus or boron was taken into the gate SiO.sub.2 film which degraded the characteristics and the reliability of each PROM cell transistor. The invention grows the BPSG film after the first and second gate insulating film is formed. Hence phosphorus or boron contained in the BPSG film is not taken into both of the gate insulating films.
REFERENCES:
patent: 5087584 (1992-02-01), Wadt et al.
Fourson George
NEC Corporation
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