Static information storage and retrieval – Read/write circuit – Precharge
Reexamination Certificate
2001-06-28
2002-11-05
Zarabian, A. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Precharge
C365S154000
Reexamination Certificate
active
06477097
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a data backup memory that temporarily stores input data synchronously with a lock signal like a flip flop that is implemented by means of a semiconductor integrated circuit.
BACKGROUND OF THE INVENTION
In recent years, technologies for semiconductor integrated circuits such as LSIs have been significantly improved, with their operating frequencies remarkably increased. However, further improvement of the performance of semiconductor integrated circuits is continuously demanded; power consumption is required to be lower, and operations are required to be faster. That is, for design of semiconductor integrated circuits, both faster operations and lower power consumption are required.
One of the basic elements constituting such a semiconductor integrated circuit is a data backup memory operating synchronously with a clock signal; such a data backup memory is represented by a flip flop. That data backup memory is a very basic circuit for a semiconductor integrated circuit, so that various circuits have been proposed to increase the operation speed and reduce the power consumption. An example of known data backup memories is U.S. Pat. No. 5,917,355 entitled “Edge-triggered staticized dynamic flip-flop with conditional shut-off mechanism”.
The conventional data backup memory as described above will be described below with reference to drawings.
FIG. 7
is a circuit diagram showing the configuration of a conventional data backup memory. In this figure, reference numeral
1001
denotes a P channel transistor that remains on to precharge a first precharge node
1041
while a clock signal terminal (CK)
1031
is set to zero. Reference numerals
1021
and
1022
denote inverters that delay a signal from the clock signal terminal (CK)
1031
for a fixed period of time to generate a delayed clock signal (CKD)
1042
. Reference numeral
1027
denotes a two-input logical-AND denying circuit using the first precharge node
1041
and the delayed clock signal (CKD)
1042
as an input and using a stop signal (S)
1043
as an output. The stop signal (S)
1043
from the circuit
1042
is set to zero only while both the first precharge node
1041
and the delayed clock signal (CKD)
1042
are set to one.
Reference numerals
1011
to
1013
denote N channel transistors connected together in series and which discharge the first precharge node
1041
when all of them are on. Specifically, if the first precharge node
1041
is set to zero or the delayed clock signal (CKD)
1042
is set to zero, and when the N channel transistor
101
is on and an input data terminal (D)
1033
is set to one, the N channel transistor
1012
is turned on. In this case, when the clock signal terminal (CK)
1031
is set to one, the N channel transistor
1013
is turned on.
Reference numerals
1023
and
1024
denote inverters that can retain the value for the first precharge node
1041
softly. When the P channel transistor
1001
is turned on, the first precharge node
1041
is precharged. When all the N channel transistors
1011
to
1013
are turned on, the first precharge node
1041
is discharged. The term “retain softly” means that the value for the first precharge node
1041
is retained when the P channel transistor
1001
is off and when at least one of the N channel transistors
1011
to
1013
is off.
Reference numeral
1002
denotes a P channel transistor that remains on to precharge the second precharge node
1051
while the first precharge node
1041
is set to zero. Reference numerals
1014
and
1015
denote N channel transistors connected together in series and which discharge a second precharge node
1051
when both of them are on. Specifically, if the clock signal terminal (CK)
1031
is set to one, the N channel transistor
1015
is turned on. If the first precharge node
1041
is set to one, the N channel transistor
1014
is turned on.
Reference numerals
1025
and
1026
denote inverters that can retain the value for the second precharge node
1051
softly.
The conventional data backup memory configured as described above constitutes a flip flop that writes a value to the input data terminal (D)
1033
at a rising edge of the clock signal terminal (CK)
1031
. Specific operations of the data backup memory will be described below.
First, the operation performed while the clock signal from the clock signal terminal (CK)
1031
is zero will be described.
At this time, the P channel transistor
1001
is on, the N channel transistor
1013
is off, and the first precharge node
1041
is set to one because a precharge path is open, while a discharge path is closed.
At this time, since the first precharge node
1041
is set to one, while the clock signal terminal (CK)
1031
is set to zero, both the precharge path and the discharge path are closed, so that the inverters
1023
and
1024
retain the previous value of the second precharge node
1051
softly.
Next, the operation performed after the clock signal has risen from zero to one and before the delayed clock (CKD)
1042
rises from zero to one will be described.
At this time, the P channel transistor
1001
is off, and the N channel transistor
1013
is on. In the first precharge node
1041
, the precharge path is closed, and the discharge path is open when the input data terminal (D)
1033
is set to one, and is closed when the input data terminal (D)
1033
is set to zero.
That is, when the input data terminal (D)
1033
is set to one, the first precharge node
1041
is discharged. When the input data terminal (D)
1033
is set to zero, both the precharge path and the discharge path are closed, so that the inverters
1023
and
1024
retain value for the first precharge node
1041
softly.
In other words, if the input data is one, a value zero is written to the first precharge node
1041
. If the input data is zero, a value one is written to the first precharge node
1041
.
Further, when the value zero is written to the first precharge node
1041
, the P channel transistor
1002
is turned on, while the N channel transistor
1014
is turned off, so that the value one is written to the second precharge node
1051
. When the value one is written to the first precharge node
1041
, the P channel transistor
1002
is turned off, while the N channel transistor
1015
is turned on. Since the N channel transistor
1014
is on, the value zero is written to the second precharge node
1051
.
Finally, a description will be given of the operation performed when the clock signal is one and when the delayed clock signal (CKD)
1042
is one.
At this time, if the first precharge node
1041
is set to one, the stop signal (S)
1043
is zero. Accordingly, in the first precharge node
1041
, since both the precharge path and the discharge path are closed, the inverters
1023
and
1024
retain the value one softly. If the first precharge node
1041
is set to zero, the precharge path is closed whether the discharge path is open or closed, so that the first precharge node
1041
is set to zero.
Further, when the first precharge node
1041
is set to, zero, the P channel transistor
1002
is turned on, while the N channel transistor
1014
is turned off, so that the second precharge node
1051
is set to one. When the first precharge node
1041
is set to one, the P channel transistor
1002
is turned off, the N channel transistor
1015
is turned on and the N channel transistor
1014
is turned on, so that the second precharge node
1051
is set to zero.
As described above, in the conventional data backup memory configured as described above, the value for the input data terminal (D)
1033
is written to the memory synchronously with the rising edge of the clock signal from the clock signal; terminal (CK)
1031
, whereas the data retaining operation is performed during the other periods.
In this case, the value of the second precharge node
1051
is output from the output data terminal (Q)
1034
as an output data signal.
Due to the constitutional characteristic (the N channel transistor
1012
to which the input d
Matsushita Electric - Industrial Co., Ltd.
Zarabian A.
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