Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch
Reexamination Certificate
2009-12-29
2011-12-06
Tran, Michael (Department: 2827)
Static information storage and retrieval
Read/write circuit
Having particular data buffer or latch
C365S194000
Reexamination Certificate
active
08072822
ABSTRACT:
A data alignment circuit of a semiconductor memory apparatus includes: a data strobe clock phase control block configured to control a phase of a data strobe clock signal in response to a strobe delay code and generate a delayed strobe clock signal; a plurality of data phase control blocks configured to control phases of input data in response to data delay codes and generate delayed data; a plurality of data alignment blocks configured to latch the delayed data in response to the delayed strobe clock signal and generate latched data and aligned data; and a delay code generation block configured to perform an operation of determining phases of the latched data and generate the strobe delay code and the data delay codes.
REFERENCES:
patent: 6026051 (2000-02-01), Keeth et al.
patent: 6160731 (2000-12-01), Choi
patent: 6349399 (2002-02-01), Manning
patent: 6636110 (2003-10-01), Ooishi et al.
patent: 6643789 (2003-11-01), Mullarkey
patent: 7224625 (2007-05-01), Dietrich et al.
patent: 2007/0257717 (2007-11-01), Yoon
patent: 2008/0181348 (2008-07-01), Best et al.
patent: 2009/0091992 (2009-04-01), Lee
patent: 11-316617 (1999-11-01), None
patent: 11-328963 (1999-11-01), None
patent: 1020090067797 (2009-06-01), None
Evelina Yeung, et al; “A 2.4 Gb/s/pin Simultaneous Bidirectional Parallel Link with Per-Pin Skew Compensation”, IEEE Journal of Solid-State Circuits, vol. 35, No. 11, Nov. 2000, (no exact date given) pp. 1619-1629.
Sung Ho Wang et al; “A 500-Mb/s Quadruple Data Rate SDRAM Interface Using a Skew Cancellation Technique”, IEEE Journal of Solid-State Circuits, vol. 36, No. 4, Apr. 2001 (no exact date given), pp. 648-657.
Jeong Chun Seok
Kim Hong Jung
Lee Jang Woo
Park Kee Teok
Yoo Chang Sik
Hynix / Semiconductor Inc.
Industry-University Cooperation Foundation Hanyang University
Tran Michael
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