Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum
Reexamination Certificate
2002-07-15
2004-01-13
Lebentritt, Michael S. (Department: 2824)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified material other than unalloyed aluminum
C257S750000, C257S774000, C257S528000, C438S597000, C438S687000
Reexamination Certificate
active
06677678
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates generally to photolithography, and more particularly, to a method of forming a damascene structure, and the structure so formed, using a sacrificial conductive layer to provide a uniform focus plane for the photolithography tool.
2. Related Art
Damascene structures are constructed by the formation of circuit features within a dielectric layer of a semiconductor wafer. The circuit features are typically trenches and/or vias, for wiring and contacts, respectively. A single-damascene structure contains only one type of circuit feature, while a dual-damascene structure contains both types of circuit features. It is also possible to form damascene structures having more than two types of circuit features.
The circuit features of the damascene structures are typically formed by first depositing a layer of photoresist over the wafer dielectric layer. The layer of photoresist is then patterned using a photolithography tool. In particular, a coherent beam of light is targeted at the surface of the wafer, the photoresist is selectively developed or removed from the wafer, thus forming a specified pattern thereon. The dielectric layer is etched to form the desired circuit features therein. The layer of photoresist is then removed, thereby forming the first circuit features. In the formation of a single-damascene structure, the circuit features are then filled with a conductive material, and planarized.
In the alternative, the creation of a dual-damascene structure requires the formation of second circuit features following the etch step described above. In particular, a second layer of photoresist is deposited over the surface of the etched dielectric layer. The second layer of photoresist is patterned, and developed again using the photolithography tool. The dielectric layer is etched, generally to a different depth than that of the first circuit features, to form a plurality of second circuit features. In the event the first circuit features are trenches, the second circuit features are vias, and vice versa. A conductive material is then deposited over the surface of the wafer, filling both circuit features. The surface of the wafer is then planarized to form a damascene structure having wiring and/or contacts therein. Both single- and dual-damascene processing are commonly employed to fabricate damascene wires and vias.
Problem Description
The single- and dual-damascene patterning steps, however, are often difficult because some photolithography tools utilize capacitive sensors to determine the focus, or the distance between the light source of the photolithography tool and the wafer, necessary to pattern the desired circuit features. The capacitive sensors typically focus on metal layers customarily embedded within the dielectric layer of conventional wafers. In the event these metal layers are not connected to the substrate, commonly referred to as “floating” layers, the photolithography tool will not completely focus on these metal layers. In addition, because the local metal wiring layout density or pattern factor can vary between 0% and 100%, the capacitive sensor may focus on an underlying layer of metal or the substrate. This may lead to systematic errors in the measured focus.
As a result, in regions of the wafer where the focus is above or below the desired location, or “focus plane,” the images produced may be printed smaller or larger than desired, may be printed with tapered resist profiles (i.e., less than 90 degree resist sidewall slopes), may be printed such that the developer does not fully remove the resist in the bottom of the feature, or may not be printed at all. Small or missing features formed therefrom, commonly referred to as “open” features, typically fail to provide the requisite electrical contact. Similarly, large features formed therefrom are commonly referred to as “blown” features, and often lead to shorts between adjacent features.
Accordingly, there exists a need in the industry for a method of accurately forming trenches and vias within damascene structures.
SUMMARY OF THE INVENTION
The present invention generally provides a method of forming a damascene structure, using a sacrificial conductive layer to provide the photolithography tool with a uniform focus plane during the formation of circuit features.
The first general aspect of the present invention provides a method of forming a damascene structure, comprising the steps of: providing a substrate having an insulative layer; depositing a sacrificial conductive layer on the insulative layer; and forming at least one circuit feature within the insulative layer. This aspect allows for more accurate formation of circuit features, e.g., trenches and vias, within a damascene structure, whether single- or dual-damascene. In particular, the sacrificial conductive layer provides the photolithography tool, used to pattern the trenches and vias, with a uniform focus plane.
The second general aspect provides a method of forming damascene lines within an insulated substrate, comprising the steps of: depositing a sacrificial conductive layer on the insulated substrate; and forming at least one circuit feature within the insulated substrate, using a patterning tool, wherein the sacrificial conductive layer provides a uniform focus plane for the patterning tool. This aspect allows for advantages similar to those associated with the first general aspect.
The third general aspect provides a damascene structure having a sacrificial conductive layer therein providing a uniform focus plane for a photolithography tool during patterning of an at least one circuit feature. This aspect provides a single- or dual-damascene structure produced using the method of the first and second aspects, and having similar advantages.
The fourth general aspect provides a damascene structure comprising: a substrate having an insulative layer; a sacrificial conductive layer on the insulative layer; and at least one circuit feature within the insulative layer of the substrate. This aspect also provides a single- or dual-damascene structure produced using the method of the first and second aspects, and having similar advantages.
The fifth general aspect provides a sacrificial conductive layer used in the formation of a damascene structure, wherein the sacrificial conductive layer provides a uniform focus plane during the formation of an at least one circuit feature. This aspect also provides a single- or dual-damascene structure produced using the method of the first and second aspects, and having similar advantages.
The foregoing and other features and advantages of the invention will be apparent from the following more particular description of preferred embodiments of the invention.
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Biolsi Peter E.
Jankowski Gregory S.
Krywanczyk Laurie M.
Stamper Anthony K.
Lebentritt Michael S.
Sabo William D.
Schmeiser Olsen & Watts
Smith Brad
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