Damascene process for reduced feature size

Details Damascene process for reduced feature size Damascene process for reduced feature size

1997-11-19

2000-06-20

Niebling, John F.

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

438638, 438639, 438640, 438666, 438668, H01L 214763

Patent

active

060777737

ABSTRACT:
Submicron contacts/vias and trenches are provided in a dielectric layer by forming an opening having an initial dimension and reducing the initial dimension by depositing a second dielectric material in the opening.

REFERENCES:
patent: 4641420 (1987-02-01), Lee
patent: 4944836 (1990-07-01), Beyer et al.
patent: 5117273 (1992-05-01), Stark et al.
patent: 5262354 (1993-11-01), Cote et al.
patent: 5488242 (1996-01-01), Sunouchi et al.
patent: 5602423 (1997-02-01), Jain
"Method to produce sizes in openings in photo images smaller than lithographic minimum size", IBM Technical Disclosure Bulletin, vol. 29, No. 3, Aug. 1986, pp. 1328.
Kaanta et al., Dual Damascene: A ULSI Wiring Technology, Proceedings of the 8th International IEEE VLSI Multilevel Interconnection Conference, Jun. 11-12, 1991, pp. 144-152.

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