Damascene process for forming ferroelectric capacitors

Details Damascene process for forming ferroelectric capacitors Damascene process for forming ferroelectric capacitors

1999-11-23

2001-05-29

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

Reexamination Certificate

active

06238963

ABSTRACT:

TECHNICAL FIELD
The field of the invention is that of forming capacitors in integrated circuits, in particular ferroelectric capacitors having noble metals as electrodes.
BACKGROUND OF THE INVENTION
Ferroelectric dielectrics such as barium strontium titanate (BST) have been suggested as capacitor dielectrics (DRAM storage capacitors or coupling capacitors in general circuits) in submicron integrated circuits because of their high dielectric constant. In addition, materials such as lead zirconium titanate (PZT) or strontium bismuth tantalate (SBT) that can store charge permanently may be used for non-volatile memories.
Their chemical properties, e.g. reactive nature, require that they be used with noble metals such as Pt or Ir.
These metals, however, are difficult to process by conventional reactive ion (dry) etching.
SUMMARY OF THE INVENTION
The invention relates to a method of forming the elements of a ferroelectric capacitor that avoids etching the noble-metal electrodes by using a damascene process and chemical-mechanical polishing to remove material outside the damascene aperture. A feature of the invention is the formation of a lower electrode in a first supporting dielectric, having a flat central portion and outer vertical walls extending to the top of the first supporting dielectric, over which a ferroelectric dielectric is deposited in a larger upper aperture, formed in a second supporting dielectric, so that the ferroelectric dielectric extends outwardly over the top of the lower electrode walls along the upper surface of the first supporting dielectric to an outer wall of the upper aperture. The result of this structure is that the upper electrode has a flat central portion over the lower electrode and a rim extending outwardly past the central portion. A lower wall connects the central portion to the rim and an upper wall extends upwardly from the rim to the top surface of the second supporting dielectric.


REFERENCES:
patent: 6015986 (2000-01-01), Shuegraf
patent: 6049103 (2000-04-01), Horikawa et al.
patent: 6051858 (2000-04-01), Uchida et al.

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