Damascene patterning of barrier layer metal for C4 solder bumps

Details Damascene patterning of barrier layer metal for C4 solder bumps Damascene patterning of barrier layer metal for C4 solder bumps

2007-02-13

2007-02-13

Thai, Luan (Department: 2891)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Ball or nail head type contact, lead, or bond

C257S780000, C257S738000, C257SE23021, C257SE23069

Reexamination Certificate

active

10710562

ABSTRACT:
A system and method for forming a novel C4solder bump for BLM (Ball Limiting Metallurgy) includes a novel damascene technique is implemented to eliminate the Cu undercut problem and improve the C4pitch. In the process, a barrier layer metal stack is deposited above a metal pad layer. A top layer of the barrier layer metals (e.g., Cu) is patterned by CMP. Only bottom layers of the barrier metal stack are patterned by a wet etching. The wet etch time for the Cu-based metals is greatly reduced resulting in a reduced undercut. This allows the pitch of the C4solder bumps to be reduced. An alternate method includes use of multiple vias at the solder bump terminal.

REFERENCES:
patent: 5298459 (1994-03-01), Arikawa et al.
patent: 5376584 (1994-12-01), Agarwala
patent: 6332988 (2001-12-01), Berger, Jr. et al.
patent: 6415974 (2002-07-01), Jao
patent: 6426556 (2002-07-01), Lin

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