Damascene pattering of SOI MOS transistors

Details Damascene pattering of SOI MOS transistors Damascene pattering of SOI MOS transistors

1997-10-22

1999-04-06

Niebling, John F.

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

On insulating substrate or layer

438151, 438412, 438430, 438164, 438589, H01L 2100

Patent

active

058917632

ABSTRACT:
The present invention is a technique for producing planar silicon on insulator MOS transistors, where the channel regions are created in an underlying single crystal silicon wafer, and where the source-drain extension regions are created by damascene patterning a thin film of amorphous silicon deposited on a layer of oxide deposited on the silicon wafer.

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