Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1998-03-06
2001-08-28
Bowers, Charles (Department: 2823)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S633000, C438S637000, C438S638000
Reexamination Certificate
active
06281121
ABSTRACT:
BACKGROUND OF THE INVENTION
As semiconductor device geometries continue to scale down below 0.5 um and approach 0.18 um minimum feature size, the metal interconnect lines which carry current between devices on a chip begin to dominate the overall circuit speed. In order to enhance interconnect speed and reliability, the semiconductor industry is moving away from blanket deposition and etch of aluminum-based metalizations, and towards damascene and dual-damascene interconnect structures with copper-based metalizations. One reason for this movement is that copper is a lower resistivity metal than aluminum, which results in a lower RC interconnect delay. Copper has also been shown to have superior electromigration performance compared to aluminum. However, copper is more difficult to process, primarily because it is more difficult to etch and it acts as a deep level trap in silicon-based devices.
The typical way to process copper interconnects in a semiconductor device is to (i) etch a trench or via into a dielectric material, (ii) deposit the interconnect metalization to fill the trench or via, and then (iii) polish the metal back to remove any metal from the field (i.e., the surface of the semiconductor wafer). The resulting metal-filled trenches or vias form the electrical interconnect. Forming an interconnect structure by filling a trench or via with metal is known as a “damascene” process. If a trench and underlying via are filled simultaneously, it is known as a dual-damascene process.
The crystallographic texture of metal interconnects can correlate very strongly to electromigration reliability. Aluminum and copper-based metal lines with strong (111) texture show better electromigration performance. Strong texture can be obtained by using, a refractory underlying metal. For example, titanium is often used a barrier/shunt layer under aluminum metalizations because the (0002) texture of the titanium induces a strong (111) texture in the overlaying aluminum-based film. In a similar way, the (0002) texture of tantalum can improve the (111) texture of copper-based metalizations. Copper interconnects with (111) texture thus show a tenfold increase in electromigration reliability as compared to randomly oriented or (100) textured copper lines.
A refractory metal such as titanium, titanium nitride, tantalum, tantalum nitride, or tungsten nitride is typically deposited prior to the deposition of aluminum or copper-based metalizations in damascene processing. This barrier layer prevents copper diffusion into the surrounding dielectric and improves the quality of the metal/dielectric interface. In order to obtain adequate step coverage in high aspect ratio trenches and vias, several deposition techniques have been developed to give very directional deposition including, for example, the use of Ionized Metal Plasma, high target-to-substrate distance, or Hollow Cathode Magnetron. Typically, these deposition techniques are optimized to give the maximum step coverage on all surfaces inside the damascene structure.
The (111) texture of aluminum-based and copper-based damascene interconnects, however, degrades with decreasing line width. Narrow lines show a (100) component which can be attributed to (111) oriented grains growing from the side of the damascene trench, such that the (100) grain orientation is parallel to the top surface of the trench. Interconnect reliability is negatively affected by the presence of these non-(111) grains. What is lacking in the art is the use of a highly directional barrier metal deposition technique to enhance the texture of the subsequently deposited metalization from only the bottom of a damascene structure (and on the field or surface of the dielectric).
SUMMARY OF THE INVENTION
In view of the above, an improved damascene metal interconnect, and method for forming the improved damascene metal interconnect, is provided. According to the method of the invention, a damascene structure is first etched into a dielectric material. A first barrier material is then deposited over the damascene structure in a manner to ensure maximized bottom and side wall coverage. A second barrier material is then deposited using a highly directional deposition technique to provide very little side wall coverage. A metalization layer is then deposited over the damascene structure, and a chemical mechanical polish is used to form the interconnect structure. The metalization layer can be either aluminum or copper-based.
The improved damascene metal interconnect includes a dielectric material, and a damascene structure etched in the dielectric material. A first barrier material is deposited on the damascene structure to ensure maximized bottom and side wall coverage. A second barrier material is applied to the first barrier material using a highly directional deposition technique to provide very little side wall coverage. A metalization layer is then deposited over the damascene structure, which can be polished using a chemical mechanical polish. The metalization layer can comprise either aluminum or copper-based metal.
The present invention provides improved texture of damascene interconnects, which can be correlated to improved electromigration reliability. In addition, the invention provides improvements to via contact resistance (analogous to graded ARC) with minimum impact on via diameter. These and other features and advantages of the invention will become apparent upon a review of the following detailed description of the presently preferred embodiments of the invention taken in conjunction with the appended drawings.
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Brown Dirk Dewar
Morales Guarionex
Nogami Takeshi
Advanced Micro Devices , Inc.
Bowers Charles
Brewster William M.
Eschweiler & Associates LLC
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