Damascene isolation of CMOS transistors

Details Damascene isolation of CMOS transistors Damascene isolation of CMOS transistors

1998-03-23

1999-11-09

Brown, Peter Toby

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438298, 438443, 438482, 438692, 148DIG1, 148DIG51, 148DIG85, 148DIG117, H01L 218238

Patent

active

059813261

ABSTRACT:
This invention is a processing method for electrically isolating CMOS transistors. The method involves implanting a channel stop dopant into field regions between transistor active regions, self aligning relatively thick silicon dioxide over these field regions and providing thin oxide in the active regions that are self aligned to the field regions. The method does not require any shallow trench isolation (STI), and does not require Local Oxidation of Silicon (LOCOS), thereby resulting in little damage to the silicon.

REFERENCES:
patent: 4110899 (1978-09-01), Nagasawa et al.
patent: 4412375 (1983-11-01), Matthews

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