Damascene gate process

Details Damascene gate process Damascene gate process

2006-01-10

2006-01-10

Wilson, Christian D. (Department: 2891)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S301000, C257S408000

Reexamination Certificate

active

06984566

ABSTRACT:
The invention provides a damascene gate process. A semiconductor substrate having a pad layer and an etch stop layer formed thereon is provided, and an insulating layer is formed to cover the etch stop layer, followed by forming an opening by partially removing the insulating layer, the etch stop layer, and the pad layer. A protective spacer is formed on the sidewall of the opening, wherein the top of the protective spacer is lower than the insulating layer. A gate conducting layer is then formed in the opening. The protective spacer and the insulating layer are removed to expose a portion of the semiconductor substrate and the etch stop layer. Implantation is then performed to form lightly doped drains. A gate spacer is then formed to cover the gate conducting layer. The etch stop layer and the pad layer are removed, and implantation is then performed to a form source/drain.

REFERENCES:
patent: 6475916 (2002-11-01), Lee et al.
patent: 6566215 (2003-05-01), Chong et al.
patent: 6674139 (2004-01-01), Mandelman et al.
patent: 2004/0135212 (2004-07-01), Dokumaci et al.

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