Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2006-07-25
2006-07-25
Tran, Mai-Huong (Department: 2818)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C257S063000, C257S065000, C257S192000
Reexamination Certificate
active
07081387
ABSTRACT:
A multi-mesa FET structure with doped sidewalls for source/drain regions and methods for forming the same are disclosed. The exposure of the source and drain sidewalls during the manufacture enables uniform doping of the entire sidewalls especially when geometry-independent doping methods, such as gas phase doping or plasma doping, is used. The resulting device has depth independent and precisely controlled threshold voltage and current density and can have very high current per unit area of silicon as the mesas can be very high compared with mesas that could be formed in prior arts. Methods of providing multi-mesa FET structures are provided which employ either a damascene gate process or a damascene replacement gate process instead of conventional subtractive etching methods.
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B.J. Machesney, et al., “Corner Enhanced Field-Effect Transistor”, IBM Technical Disclosure Bulletin, vol. 34, No. 12, May 1992 (pp. 101-102).
Furukawa Toshiharu
Mandelman Jack A.
Park Byeongju
Abate Esq. Joseph P.
International Business Machines - Corporation
Scully , Scott, Murphy & Presser, P.C.
Tran Mai-Huong
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