Damascene formation of borderless contact MOS transistors

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

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Details

438221, 438299, 438303, 438585, H01L 218238

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active

060157275

ABSTRACT:
This invention is a processing method for forming MOS transistors. The method uses chemical mechanical polishing to self align an MOS transistor gate electrode to the channel region in both the width and length directions. The method enables metal interconnect lines to make borderless connections to MOS gate electrodes directly over channel regions, and allows borderless connections to be made to source and drain regions, thereby improving layout density of small transistors. The method enables interconnect lines to be patterned on a planar surface, which facilitates the etching of very narrow and closely spaced lines. The method does not require any Shallow Trench Isolation (STI), and does not require Local Oxidation of Silicon (LOCOS), thereby resulting in little damage to the silicon. The method also prevents plasma damage of very thin gate dielectrics during processing.

REFERENCES:
patent: 5028555 (1991-07-01), Haskell
patent: 5721173 (1998-02-01), Yano et al.
patent: 5770485 (1998-06-01), Gardner et al.
patent: 5780325 (1998-07-01), Lee
patent: 5851883 (1998-12-01), Gardner et al.
patent: 5904529 (1999-05-01), Gardner et al.

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