Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2003-06-30
2004-12-28
Nadav, Ori (Department: 2811)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S149000, C438S479000
Reexamination Certificate
active
06835614
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to semiconductor devices, and more particularly to a method of fabricating a double-gated metal oxide semiconductor field effect transistor (MOSFET) structure that has sub-0.05 &mgr;m channel lengths associated therewith. The present invention also relates to a double-gated MOSFET structure having vertical channel regions. The structure of the inventive MOSFET comprises a silicon film having a vertical thickness of about 80 nm or less which forms the vertical body, i.e., vertical channels, of the structure.
BACKGROUND OF THE INVENTION
Over the past twenty-five years or so, the primary challenge of very large scale integration (VLSI) has been the integration of an ever-increasing number of MOSFET devices with high yield and reliability. This was achieved mainly in the prior art by scaling down the MOSFET channel length without excessive short-channel effects. As is known to those skilled in the art, short-channel effects are the decrease of threshold voltage V
t
in short-channel devices due to two-dimensional electrostatic charge sharing between the gate and the source/drain regions.
To scale down MOSFET channel lengths without excessive short-channel effects, gate oxide thickness has to be reduced while increasing channel-doping concentration. However, Yan, et al., “Scaling the Si MOSFET: From bulk to SOI to bulk”, IEEE Trans. Elect. Dev., Vol. 39, p. 1704, July 1992, have shown that to reduce short-channel effects for sub-0.05 &mgr;m MOSFETs, it is important to have a backside-conducting layer present in the structure that screens the drain field away from the channel. The Yan, et al. results show that double-gated MOSFETs and MOSFETs with a top gate and a backside ground plane are more immune to short-channel effects and hence can be scaled to shorter dimensions than conventional MOSFETs.
The structure of the prior art MOSFETs consists of a very thin insulating layer for the channel, with two gates, one on each side of the channel. The two gates are electrically connected so that they serve to modulate the channel. Short-channel effects are greatly suppressed in such a structure because the two gates very effectively terminate the drain field line preventing the drain potential from being felt at the source end of the channel. Consequently, the variation of the threshold voltage with drain voltage and with gate length of a prior art double-gated MOSFET is much smaller than that of a conventional single-gated structure of the same channel length.
To date, there are no adequate means for fabricating double-gated MOSFET structures, thus there is a continued need for developing a new and improved method of fabricating double-gated MOSFETs in which the variation of the threshold voltage with drain voltage and with gate length is substantially less than that of a single-gated structure of the same channel length. Moreover, there is a continued need for developing a method of fabricating a double-gated structure having an on-current that is double that of a single-gated structure with the same channel length.
SUMMARY OF THE INVENTION
One object of the present invention is to provide a method of fabricating a double-gated/double channel MOSFET structure that has sub-0.05 &mgr;m channels length associated therewith.
Another object of the present invention is to provide a method of fabricating a double-gated/double channel MOSFET structure that has excellent short-channel characteristics.
A further object of the present invention is to provide a method of fabricating a double-gated/double channel MOSFET structure in which the variation of threshold voltage with drain voltage and with gate length is substantially less than that of a single-gated structure of the same channel length.
A yet further object of the present invention is to provide a method of fabricating a double-gated/double channel MOSFET structure which has double the on-current as compared with conventional single-gated structures of the same channel length.
These and other objects and advantages are achieved in the present invention by utilizing a damascene process for the fabrication of a MOSFET structure with a double-gated/double channel structure; the gate of the inventive device is located on each side of a silicon film having a vertical thickness, i.e., height, on the order of about 80 nm or less. The silicon film, which is formed on top of an insulating region, functions as the vertical channel regions of the MOSFET structure and it is surrounded with a gate forming a MOSFET structure with two parallel channels and a single-gate.
Short-channel effects are greatly reduced with sub-0.05 &mgr;m channel lengths because the device body, i.e., channel regions, has a very thin horizontal thickness which allows the termination of the drain field lines on the surrounding gate. This, in turn, prevents the drain potential from being felt at the source end of the channel. The current of the inventive structure is double that of a conventional planar MOSFET with the same physical channel length due to its dual channel feature.
One aspect of the present invention thus relates to a method of fabricating a double-gated/double channel MOSFET structure having sub-0.05 channel lengths, said method comprising the steps of:
(a) forming a patterned hard mask on a surface of a substrate, said substrate comprising at least a silicon layer formed on top of an insulating region;
(b) forming a patterned dummy gate stack on a portion of said silicon layer and a portion of said patterned hard mask;
(c) forming source/drain extensions by removing said silicon layer not protected by said hard mask and said patterned dummy gate stopping on said insulating region and oxidizing exposed sidewalls of said silicon layer protected by said hard mask and said patterned dummy gate region;
(d) forming an oxide layer on exposed surfaces of said insulating region and planarizing said oxide layer stopping on an uppermost polysilicon surface of said patterned dummy gate;
(e) removing said patterned dummy gate stopping on said hard mask so as to provide an opening in said oxide layer;
(f) forming a gate stack in said opening; and
(g) removing said oxide layer and said hard mask abutting said gate stack so as to expose said insulating region and portions of said silicon layer abutting said gate stack.
In the above-described method, the silicon layer that remains under the hard mask in the opening provided in step (e) represents the vertical channel regions of the inventive double-gated/double channel MOSFET structure.
Following step (g) above, the present invention also contemplates one or more of the following steps:
forming activated source/drain regions in portions of said exposed silicon layer abutting said gate stack.
subjecting said gate stack to oxidation (required if the gate stack comprises polysilicon).
forming spacers on exposed sidewalls of said gate stack (optional for polysilicon-containing gate stacks, but required for non-polysilicon gate stacks).
saliciding said source/drain regions, or forming raised source/drain regions on portions of said exposed silicon layer abutting the gate stack and then saliciding the raised source/drain regions.
further back-end-of the line (BEOL) processing.
Another aspect of the present invention comprises a double-gated/double channel MOSFET structure which is formed from the above-mentioned processing steps. Specifically, the inventive double-gated/double channel MOSFET structure comprises:
a bottom Si-containing layer;
an insulating region present on said bottom Si-containing layer;
a top silicon layer present on a portion of said insulating region, wherein a portion of said top silicon layer functions as vertical channel regions and other portions of said top silicon layer abutting said vertical channel regions contain diffusion regions therein;
a hard mask formed on top of said vertical channel regions; and
a gate region formed surrounding said vertical channel regions, wherein said gate region includes at least a gate oxide formed on exposed sidewalls of
Brown Jeffrey J.
Hanafi Hussein I.
Natzle Wesley C.
Cheung, Esq. Wan Yee
Nadav Ori
Scully Scott Murphy & Presser
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