Damage free passivation layer etching process

Radiation imagery chemistry: process – composition – or product th – Imaging affecting physical property of radiation sensitive... – Making electrical device

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216 41, 216 67, 216 72, 430317, 438714, 438738, G03F 740, G03F 736, B44C 122, C03L 1500, C23F 100

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060015381

ABSTRACT:
A method for etching bonding pad access openings in a passivation layer of an integrated circuit is described. The method utilizes a two step etching procedure wherein the first step etches isotropically through a major portion of the passivation layer under conditions which provide very high etch rate selectivities of the passivation material to the photoresist. These high selectivitities result in virtually no erosion of the photoresist while the greater part of the opening is etched. A second anisotropic etch step wherein the base of the access opening is defined faithfully replicates the dimensions of the mask pattern. This two step etch process permits the use of photoresist layers of moderate thickness as well as photoresist layers with thin regions, such as occur when the photoresist is deposited over the uneven surface topography typically found on unplanarized passivation layers. The minimal erosion of the photoresist during the isotropic etch step secures sufficient photoresist coverage in the thin regions to prevent penetration and attack of passivation over wiring lines in the uppermost wiring level of the integrated circuit.

REFERENCES:
patent: 4764245 (1988-08-01), Grewal
patent: 5182234 (1993-01-01), Meyer
patent: 5296094 (1994-03-01), Shan et al.
patent: 5549784 (1996-08-01), Carmody et al.
"USLI Technology" by C.Y. Chang et al., The McGraw-Hill Companies, Inc, New York, 1997, p. 354.

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