Active solid-state devices (e.g. – transistors – solid-state diode – Lead frame – With dam or vent for encapsulant
Reexamination Certificate
2001-07-17
2003-04-29
Lee, Eddie (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Lead frame
With dam or vent for encapsulant
C257S787000, C257S777000, C438S112000, C438S124000, C438S127000, C438S106000
Reexamination Certificate
active
06555898
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention generally relates to packaging for a semiconductor chip and is particularly directed to providing a chip scale package for a chip. In certain embodiments, the invention relates to a packaging system that blocks encapsulant from flowing beyond areas intended to be encapsulated. The invention is particularly well suited for encapsulating connections formed between chip bonding pads and leads on a flexible substrate in a chip scale package.
After a chip is fabricated on a wafer and separated therefrom, it is packaged for protection and to facilitate its integration into a circuit on a printed circuit board (“PCB”), flexible printed circuit (“FPC”), or other board or electronic product (hereinafter such products are collectively referred to as “circuitry products”). The package also provides the chip (1) a lead system for connecting the chip to a PCB or other product; (2) physical protection; (3) environmental protection; and (3) a mechanism for heat dissipation. A package typically includes an enclosure or body, which may also be referred to herein as an “interposer.” Enclosures may be made of ceramic, epoxy, and flexible substrates based on polyimide, for example. The enclosure also includes an inner lead system for electrically connecting to bonding pads on the chip and an outer lead system for electrically connecting the packaged chip to a circuitry product. Conductive traces may also be included between inner and outer lead systems.
Numerous packaging techniques exist. Generally, each involves putting the chip into an individual package, which can be connected directly to a circuit board; putting the chip into a multichip module (“MCM”) with other chips that are packaged together; or using direct chip attachment (“DCA”) to connect the chip to a circuitry product.
The chip may be electrically connected to the inner lead system of the package via bonding wires, solder balls, or other chip connectors bonded to the bonding pads of the chip. Typically, the chip's bonding pads are in an array along outer edges of the chip. However, as discussed in more detail below, a chip may have its bonding pads arrayed off the edges, for example, in the center of the chip.
The bonds formed between the chip bonding pads and the package lead system is typically covered or filled with an encapsulant to protect the bonds from physical and environmental damage and to preserve their function. In one conventional method suitable for use with chips having bonding pads at edges, chips are mounted upside down (circuitry side down) on a coverlay tape to encapsulate the non-circuitry side of the chip. In this process, the encapsulant flows along the tape and the chip to fill in the space left between the die and the substrate. The encapsulant is cured and the tape removed. One problem with this approach is containing the encapsulant in intended regions of application on the chip. However, liquid encapsulants pose certain problems. If the liquid is formulated too thick, it can leave voids after it solidifies. Interconnections that are covered by encapsulant having voids may not be protected adequately and may be adversely affected electrically. If encapsulant liquid is formulated too thin, it can flow beyond intended areas of the chip and interposer. Due to overflow of the encapsulant, the excess encapsulant must be trimmed off the chips. Thus to make an even-edged package, labor, time and cost are added to the packaging process.
Various forms of packaging have evolved based on the foregoing packaging fundamentals, including plastic ball grid array package (PBGA) and direct chip attach (“DCA”). Unfortunately, these and other conventional packaging techniques suffer from disadvantages. These disadvantages include excessive package size, weight, and cost. The packages may also require excessive process steps and additional equipment. These disadvantages have become particularly heightened as advancements have been made in wafer processing and chip fabrication. Packaging technology, at least initially, did not keep pace with such advances.
In reaction to the need for packaging advancements that are suitable for use with more advanced, higher density chips, the industry has developed a packaging technology called chip scale package (“CSP”). The objectives of CSP include providing a package that avoids adding size and bulk to the chip to maintain the profile of the chip. A package area that is less than 1.2 times the chip area is generally considered a CSP. See LAU et al,
CHIP SCALE PACKAGE: DESIGN MATERIALS, PROCESS, RELIABILITY, AND APPLICATIONS
(McGraw-Hill 1999), p.2. There are at least three significant advantages to employing CSP technology: higher component density, more efficient assembly automation, and enhanced product performance.
There are at least 40 types of CSP technology, some being close variations of others. Representative technologies are described in LAU et al, supra. One popular CSP technology uses a thin flexible substrate (interposer), which may be used in a process called “tape automated bonding” (TAB). TAB is particularly useful where extreme package thinness needed. In TAB bonding, an electrical lead system is formed on a thin flexible, tape-like substrate. The lead system may be formed by a patterning process similar to that used in wafer fabrication or by mechanically stamping or chemically bonding the conductive materials of the lead system on to the substrate. The resulting tape appears similar to a camera or movie film, with multiple sets of lead systems spaced along the length of the tape. Tape is provided in reels or frames for use in the packaging process. Like camera or movie film, the tape may have sprocket holes for a sprocketed tape feeder to move the tape over a chip held in a chuck or die mounter. The tape is moved until a lead system aligns with a bonding pad array on a chip. After alignment, the leads are connected to the bonding pads thermosonically with a tool called a thermode or thermosonic bonder. The thermode has a surface that is heated and moved down upon the leads on the tape. The thermode presses the leads downwardly onto the bonding pad array. The heat and pressure of the thermode bond the leads to the pads. After attachment, bonds are covered with encapsulant using a coverlay tape.
One of the better known CSP's using a flexible package is the &mgr;-BGA® flexible interposer of Tessera, in San Jose Calif. The &mgr;-BGA® interposer has ribbon-like flexible leads for chip level interconnection and a compliant elastomer between the interposer and the chip to relieve stress in the connections arising from the connected structures having different thermal expansion properties. Thermosonic bonding is used to bond the leads on the interposer to the chip's bonding pads.
One advantage of &mgr;-BGA® interposer and similar flexible interposers is that the bonding areas are not restricted to the outer edges of the chip. Thus, a flexible interposer is particularly useful in bonding chips having an array of bonding pads disposed along a central axis of the chip. Therefore, flexible interposers, such as the &mgr;-BGA®, are quite suitable for chips with center bond pads. Most DRAM chips above 16 MB fall into this category.
In many CSP processes, including TAB processes, a liquid encapsulant is applied over interconnections to protect them. The general problems of using encapsulant are applicable to CSP processes.
The encapsulation process poses significant drawbacks relative to flexible interposers for chips with center bond pads. In center bonded packages, the tape interposer overlies the entire surface of the chip, except for an opening in the interposer over the array of bond pads. After leads such as conductive ribbons or other interconnects are pressed down on the bond pads and bonded thereto, the bonds must be encapsulated. After bonding, liquid encapsulant is applied over the interconnections in a cavity defined by a floor of the top surface of the chip and sidewalls of the parallel rows of interconnect
Diaz Jose′ R.
Ganz Bradley M.
Ganz Law PC
Lee Eddie
Micro)n Technology, Inc.
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