D-FF circuit

Details D-FF circuit D-FF circuit

2001-03-27

2002-10-01

Le, Don Phu (Department: 2819)

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

Field-effect transistor

C326S113000, C327S203000

Reexamination Certificate

active

06459302

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a D-FF circuit. In particular, the present invention relates to a D-FF circuit which is operated in accordance with a clock signal generated by a clock signal generating circuit.
2. Description of the Related Art
According to an earlier development, a D-flip-flop (hereinafter, referred to as “D-FF”) made from CMOS (Complementary MOS) comprises a flip-flop for a master part (hereinafter, referred to as “master FF”), a flip-flop for a slave part (hereinafter, referred to as “slave FF”) and a clock signal generating circuit. The clock signal generating circuit generates a clock signal to output the clock signal to the master FF and the slave FF. The master FF and the slave FF start or stop each operation at each timing in accordance with the outputted clock signal, respectively.
With reference to
FIGS. 3A
,
3
B and
4
, a D-FF circuit
100
according to an earlier development, will be explained.
FIG. 3A
is a view showing a D-FF circuit
100
according to an earlier development.
FIG. 3B
is a view showing a clock signal generating circuit
200
of the D-FF circuit
100
.
In
FIG. 3A
, the D-FF circuit
100
comprises a master FF having inverters
101
and
102
, transfer gates G
1
and G
2
and a NAND gate
106
, and a slave FF having transfer gates G
3
and G
4
, a NAND gate
107
and inverters
103
,
104
and
105
. The master FF and the slave FF start or stop each operation in accordance with the clock signal outputted from the clock signal generating circuit
200
, respectively.
The transfer gates G
1
, G
2
, G
3
and G
4
comprise P-channel transistors Tr
5
to Tr
8
and N-channel transistors Tr
1
to Tr
4
, respectively. The clock signal outputted from the clock signal generating circuit
200
is inputted into each transistor Tr
1
to Tr
8
. Each transfer gate G
1
, G
2
, G
3
and G
4
is in an “ON” state or in an “OFF” state according to the clock signal inputted into each transistor Tr
1
to Tr
8
. These transfer gates hold or transmit an input signal data.
As shown in
FIG. 3B
, the clock signal generating circuit
200
comprises three inverters
31
,
32
and
33
. The inverter
31
inverts an input clock signal CLK to output a first clock signal {overscore (CLK
1
)}. The inverter
32
inverts the first clock signal {overscore (CLK
1
)} to output a second clock signal CLK
2
. The inverter
33
inverts the second clock signal CLK
2
to output a third clock signal {overscore (CLK
2
)}.
The second clock signal CLK
2
and the third clock signal {overscore (CLK
2
)} are used as clock signals for stopping the operation of the master FF. The first clock signal {overscore (CLK
1
)} and the second clock signal CLK
2
are used as clock signals for starting the operation of the slave FF.
The operation of the D-FF circuit
100
which is constructed as described above, will be explained with reference to the operation timing chart shown in FIG.
4
. In
FIG. 4
, the solid lines show the operation of the D-FF circuit
100
in the rising of the input signal data. The alternate long and short dash lines show the operation of the D-FF circuit in the falling of the input signal data.
First, the operation of the D-FF circuit in the rising of the input signal data, will be explained with reference to the waveforms drawn by the solid lines shown in FIG.
4
.
At the time t
50
, when the voltage of the input signal data rises from a “L” level to a “H” level, the inverter
101
inverts the input signal data to output a “L” level signal. At the same time, because the second clock signal CLK
2
is in a “L” level and the third clock signal {overscore (CLK
2
)} is in a “H” level, the transfer gate G
1
is in an “ON” state. Therefore, the transfer gate G
1
outputs the “L” level signal which is outputted from the inverter
101
, to the inverter
102
. The inverter
102
inverts the inputted “L” level signal to output a “H” level signal. At the time t
51
, the voltage of the signal falls from a “H” level to a “L” level at a node N
2
. At the time t
52
, the voltage of the signal rises from a “L” level to a “H” level at a node N
3
.
On the other hand, in the clock signal generating circuit
200
, at the time t
52
, the voltage of the input clock signal CLK rises from a “L” level to a “H” level. An external set up time which is the period from the time that the input data is inputted to the time that the voltage of the input clock signal rises, is from the time t
50
to the time t
52
.
The input clock signal CLK is inverted by the inverter
31
. At the time t
53
, a “L” level first clock signal {overscore (CLK
1
)} is outputted. The first clock signal {overscore (CLK
1
)} is inverted by the inverter
32
. At the time t
55
, a “H” level second clock signal CLK
2
is outputted. Because the first clock signal {overscore (CLK
1
)} is in a “L” level and the second clock signal CLK
2
is in a “H” level, the transfer gate G
3
is in an “ON” state and starts the operation of the slave FF.
When the operation of the slave FF is started at the time t
55
, a “H” level signal which passes through a node N
3
at the time t
52
, passes through the transfer gate G
3
. At the time t
57
, the voltage of the signal rises from a “L” level to a “H” level at a node N
5
.
At the time t
56
, the second clock signal {overscore (CLK
1
)} passes through the inverter
33
of the clock signal generating circuit
200
. The inverter
33
outputs a “L” level third clock signal {overscore (CLK
2
)}. Then, the transfer gate G
1
is in an “OFF” state. The operation of the master FF is stopped and the master FF holds the input signal data.
Next, the operation of the D-FF circuit in the falling of the input signal data, will be explained with reference to the waveforms drawn by the alternate long and short dash lines.
At the time t
50
, when the voltage of the input signal data falls from a “H” level to a “L” level, the inverter
101
inverts the input signal data to output a “H” level signal. At the same time, because the second clock signal CLK
2
is in a “L” level and the third clock signal {overscore (CLK
2
)} is in a “H” level, the transfer gate G
1
is in an “ON” state. Therefore, at the time t
52
, the voltage of the signal rises from a “L” level to a “H” level at the node N
2
. The signal which passes through the node N
2
, is inverted by inverter
102
. At the time t
54
, the voltage of the signal falls from a “H” level to a “L” level at the node N
3
.
On the other hand, in the clock signal generating circuit
200
, at the time t
52
, the voltage of the input clock signal rises from a “L” level to a “H” level. The input clock signal CLK is inverted by the inverter
31
. At the time t
53
, a “L” level first clock signal {overscore (CLK
1
)} is outputted. The first clock signal {overscore (CLK
1
)} is inverted by the inverter
32
. At the time t
55
, a “H” level second clock signal CLK
2
is outputted. Because the first clock signal {overscore (CLK
1
)} is in a “L” level and the second clock signal CLK
2
is in a “H” level, the transfer gate G
1
is in an “OFF” state. The operation of the master FF is stopped and the master FF holds the input signal data.
At the time t
61
, the voltage of a reset signal RB falls from a “H” level to a “L” level. Then, at the time t
62
, the voltage of the signal rises from a “L” level to a “H” level at the node N
2
. At the time t
63
, the voltage of an output signal OUT rises from a “L” level to a “H” level. An external reset time tR (the period from the time that the reset signal is inputted to the time that the output signal {overscore (OUT)} is reset) is from the time t
61
to the time t
63
.
However, in the D-FF circuit according to an earlier development, which is shown in
FIG. 3
, when the voltage of the input signal data falls, there are many cases that a current supply capacity of the P-channel transistor Tr
5
of the transfer gate G
1
is not sufficient. Therefore, the rise-time that the voltage of the signal rises at the node N
2
, is slow (long). In contrast to the P-channel transistor Tr
5
, th

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