Single-crystal – oriented-crystal – and epitaxy growth processes; – Apparatus – For crystallization from liquid or supercritical state
Reexamination Certificate
2002-08-13
2004-11-23
Hiteshew, Felisa (Department: 1765)
Single-crystal, oriented-crystal, and epitaxy growth processes;
Apparatus
For crystallization from liquid or supercritical state
C117S218000, C117S222000, C117S911000
Reexamination Certificate
active
06821344
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to microelectronic manufacturing methods and devices, and more particularly to silicon ingot manufacturing methods and silicon ingots and wafers manufactured thereby.
BACKGROUND OF THE INVENTION
Monocrystalline silicon, which is the starting material in fabricating semiconductor devices, is grown into a cylindrical ingot by a crystal growth technique, which is referred to as the Czochralski (CZ) technique. The ingot of monocrystalline silicon is processed into wafers via a series of wafering processes such as slicing, etching, cleaning, polishing and the like. According to the CZ technique, a seed crystal of monocrystalline silicon is immersed into molten silicon and pulled upwards, and the molten silicon is then grown into a monocrystalline ingot by slow extraction. The molten silicon is contained in a quartz crucible, and is contaminated with a variety of impurities, one of which is oxygen. At the melting temperature of silicon, the oxygen permeates the crystal lattice until it reaches a predetermined concentration which generally is determined by the solubility of oxygen in silicon at the melting temperature of silicon and by the actual segregation coefficient of oxygen in solidified silicon. The concentration of oxygen, which permeates the silicon ingot during crystal growth, is greater than the solubility of oxygen in solidified silicon at typical temperatures used in semiconductor device manufacture. As the crystal grows from the molten silicon and cools, the solubility of oxygen therein rapidly decreases, whereby oxygen is saturated in the cooled ingot. As a result, the saturated oxygen generates crystalline defects, referred to as “D-defects”, in the shape of void in the ingot.
Such D-defects can cause Crystal Originated Precipitates (COPs), which are pits having a {111}-plane on the surface of the wafer, to occur during a series of wafering processes such as slicing, polishing, cleaning and the like. In particular, the COPs may be enlarged through cleaning and oxidation processes, which are performed repeatedly in fabricating integrated circuit devices. The number of COPs also may sharply increase.
FIG. 1
is a sectional view of a conventional Metal Oxide Semiconductor (MOS) transistor. Referring to
FIG. 1
, when the COPs at the wafer surface exist in a channel region, which is located in an active region of the semiconductor device between a source region
12
and a drain region
14
which are formed near the surface of a silicon substrate
10
, a gate insulation layer
16
, for electrically insulating a gate electrode
18
and the silicon substrate
10
, may break down. In addition, the refresh characteristics of a memory device that uses the MOSFET may degrade. Moreover, when the COPs at the wafer surface exist in a field oxide layer, which separates active regions of the semiconductor device, impurity ions may permeate down to a bulk region below the field oxide layer during ion implantation, which may cause failure in isolation due to channeling.
Also, oxygen precipitates formed in the bulk region
10
a
of the wafer, which are produced by subsequent heat treatment, can act as a leakage source and can act as intrinsic gettering sites, which are capable of trapping unfavorable metal contaminants during subsequent semiconductor device manufacturing. Thus, if the concentration of oxygen in the ingot is high, the concentration of oxygen precipitates which act as the intrinsic gettering sites can increase, so that the gettering capability increases. However, if the concentration of oxygen is not sufficient, oxygen precipitates may not be produced in the bulk region, so that the gettering capability may be reduced or may not be present at all. Thus, it may be desirable to properly control the amount of oxygen precipitates distributed in the bulk region of the wafer.
In a wafer which is obtained by a conventional crystal growth and wafering process, oxygen precipitates distribute through the wafer, from the top (front side) surface of the bottom (back side) surface. In general, a Denuded Zone (DZ)
10
b
should be provided from the top surface to a predetermined depth, which is devoid of oxygen-related defects, such as voids, COPs, dislocations, stacking faults and oxygen precipitates. However, wafers fabricated by conventional methods may produce oxygen precipitates near the surface of the wafer, which can act as a source of leakage current.
Thus, in order to form intrinsic gettering sites in the bulk region of the wafer with a sufficient DZ near the surface of the wafer, a wafer containing a high concentration of oxygen, for example, at an initial oxygen concentration of 13 parts per million atoms (ppma) or more may be thermally processed for a long period of time by alternating the temperature between low and high levels, such that oxygen precipitates may be generated in the bulk region of the wafer, and simultaneously the oxygen precipitates present near the surface of the wafer may be out-diffused to obtain a clear DZ. In a semiconductor wafer thermally processed by this conventional technique, the oxygen precipitate concentration profile through the wafer, from the top surface to the bottom surface of the wafer, may be as illustrated in FIG.
2
.
Referring to
FIG. 2
, both the intrinsic gettering sites in the bulk region and the sufficient DZ near the surface of the wafer can be provided by the conventional technique. However, due to the additional high-temperature thermal process for a long period of time, the wafer characteristics may degrade. For example, slippage or warpage may occur in the wafer. Moreover, the manufacturing cost may increase. Also, in such a case, metal contaminants, and particularly iron (Fe), which are trapped by the oxygen precipitates in the bulk region, may be released into the DZ by a subsequent process, so that the released contaminants can act as a leakage source.
FIG. 3
is a diagram illustrating a redrawn oxygen precipitate concentration profile of a wafer fabricated by another conventional method, which is disclosed in FIG. 1A of U.S. Pat. No. 5,401,669. In particular,
FIG. 3
is the oxygen precipitate concentration profile of a wafer with respect to the depth of the wafer, resulting from a rapid thermal annealing process on a wafer carried out in a nitrogen atmosphere, and subjecting the wafer to subsequent heat treatment. However, as can be seen from
FIG. 3
, neither the DZ near the surface of the wafer nor sufficient oxygen precipitates in the bulk region may be obtained by this conventional method.
SUMMARY OF THE INVENTION
Embodiments of the present invention provide a silicon wafer having a controlled vertical distribution of oxygen precipitates which can act as intrinsic gettering sites. In particular, the oxygen precipitate concentration profile from the top surface, in which an active region of a semiconductor device may be formed, to the bottom surface of the silicon wafer, comprises first and second peaks at first and second predetermined depths from the top and bottom surfaces of the wafer, respectively. Also, a Denuded Zone (DZ) is included between the top surface of the wafer and the first peak and between the bottom surface of the wafer and the second peak. The oxygen precipitate concentration profile also has a concave region between the first and second peaks, which can correspond to a bulk region of the wafer.
In embodiments of the invention, the oxygen precipitate concentration profile is symmetrical with respect to a central surface of the silicon wafer that is centrally located between the top and bottom surfaces. Thus, for example, the first and second predetermined depths are the same. However, in other embodiments, the profile need not be symmetrical, such that, for example, different depths may be provided for the first and second peaks. Also, in some embodiments of the invention, the depth of the denuded zones is in the range of about 10 &mgr;m to about 40 &mgr;m from each surface of the silicon wafer, such that the active region of the semiconduc
Hiteshew Felisa
Myers Bigel & Sibley & Sajovec
Samsung Electronics Co,. Ltd.
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