Cycle independent data to echo clock tracking circuit

Details Cycle independent data to echo clock tracking circuit Cycle independent data to echo clock tracking circuit

1999-10-19

2000-10-17

Nelms, David

Static information storage and retrieval

Addressing

Sync/clocking

365194, G11C 800

Patent

active

061341827

ABSTRACT:
A comparator and variable delay circuit are provided to maintain the tracking between data and echo clocks in a double data rate (DDR)RAM device. This is accomplished by providing a global data signal (dummy data signal) that tracks with the actual memory array data. This global data signal is compared to the timing of the RAM clock (CLOCK) to determine a delay time between the two by which the pipeline clocks (CLKRISE/CLKFALL) must be delayed. As a result, the pipeline clocks are pushed out as needed so that they always transition after the array data arrives at the output latch. Therefore, as cycle time decreases, both echo clocks and data are pushed out identically and maintain their required tracking.

REFERENCES:
patent: 5440514 (1995-08-01), Flannagan et al.
patent: 5557781 (1996-09-01), Stones et al.
patent: 5790838 (1998-08-01), Irish et al.
patent: 5815462 (1998-09-01), Konishi et al.
patent: 5875134 (1999-02-01), Cloud
patent: 5920511 (1999-07-01), Lee et al.
G. T. Davis et al., "Digital Phase-Locked Loops Using Shared Logic, Accepting Variable Reference and System Clocks", IBM Technical Disclosure Bulletin, vol. 38, No. 9, Sep. 1995.

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