CVD plasma process to fill contact hole in damascene process

Details CVD plasma process to fill contact hole in damascene process CVD plasma process to fill contact hole in damascene process

1999-06-08

2001-02-13

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S633000

Reexamination Certificate

active

06187666

ABSTRACT:

TECHNICAL FIELD
The present invention generally relates to semiconductor processing, and in particular to a method for improving a dual damascene process.
BACKGROUND OF THE INVENTION
The escalating requirements for density and performance associated with ultra large scale integration (ULSI) circuits require responsive changes in interconnection technology which is considered a very demanding aspect of ULSI technology. High density demands for ULSI integration require planarizing layers with minimal spacing between conductive lines.
Single damascene is a technique developed to address disadvantages (e.g., poor metal step coverage, residual metal shorts, low yields, uncertain reliability, and poor ULSI integration extendability) associated with traditional etch back methods. Damascene, an art which has been employed for centuries in the fabrication of jewelry, has been adapted for application in the semiconductor industry. Damascene basically involves the formation of a trench which is filled with a metal. Thus, damascene differs from traditional etch back methods which involve building up a metal wiring layer and filling the interwiring spaces with a dielectric material.
Single damascene techniques offer the advantage of improved planarization as compared to etch back methods; however, single damascene is time consuming in that numerous process steps are required. Undesirably, an interface exists between the conductive via and conductive wiring. Moreover, adequate planarization layers containing an interwiring spacing less than 0.35 &mgr;m are difficult to achieve.
An improvement to single damascene is dual damascene which involves substantially simultaneous formation of a conductive via and conductive wiring. The dual damascene technique requires less manipulative steps than the single damascene technique and eliminates the interface between the conductive via and conductive wiring which is typically formed by the single damascene technique. In very and ultra large scale integration (VLSI and ULSI) circuits, an insulating or dielectric material, such as silicon oxide, of the semiconductor device in the dual damascene process is patterned with several thousand openings for the conductive lines and vias which are filled with metal, such as aluminum, and serve to interconnect active and/or passive elements of the integrated circuit. The dual damascene process also is used for forming multilevel signal lines of metal, such as copper, in the insulating layers, such as polyimide, of multilayer substrate on which semiconductor devices are mounted.
A conventional dual damascene process is illustrated in
FIGS. 1
a
-
1
h
in connection with a semiconductor structure
18
.
FIG. 1
a
illustrates an insulative layer
20
formed on a semiconductor substrate (not shown). A photoresist layer
22
a
is formed on the insulative layer
20
. The photoresist layer
22
a
is patterned using conventional techniques to form a first opening
30
(
FIG. 1
b
). Anisotropic reactive ion etching (RIE) is performed to form a via
40
(
FIG. 1
c
) in the insulative layer
20
. Subsequently, a second layer of photoresist
22
b
(
FIG. 1
d
) is formed over the structure
18
.
The second photoresist layer
22
b
is patterned to form a second opening
48
(
FIG. 1
e
) about the size of the ultimate trench. Anisotropic RIE is again performed to form a trench
50
(
FIG. 1
f
) in the insulative layer
20
. Although this standard dual damascene technique offers advantages over other processes for forming interconnections, it has a number of disadvantages, such as the edges of the via openings and the sidewalls of the via
40
in the lower half of the insulating layer
20
are poorly defined because of the two etchings and the via edges and sidewalls being unprotected during the second etching. More particularly, gases from the second etch step leak under photoresist portion
22
c
and damage edges and sidewalls of the via
40
as illustrated in
FIGS. 1
g
and
1
h.
In view of the above, improvements are needed to mitigate poor edge and sidewall definition of vias associated with conventional dual damascene processes.
SUMMARY OF THE INVENTION
The present invention relates to a method for mitigating poor edge and sidewall definition in vias common to conventional dual damascene processes by employing a conformal insulating layer to protect edges and sidewalls of a via from exposure to a second etch step (to form trenches). In particular, after a first etch step to define a via, a conformal layer of insulating material is formed to insulate edges and sidewalls of the via. The conformal layer protects the via edges and sidewalls from exposure to reactive gases of the second etch step. After the second etch step is substantially complete, the conformal layer is removed to leave a dual damascene structure (trench and via) which has improved via edge and sidewall definition as compared to many structures formed under conventional dual damascene methodologies.
One aspect of the invention relates to a method for fabricating interconnecting lines and vias in a layer of insulating material. A via is formed in the layer of insulating material. A protective material is formed so as to be conformal to at least edges and sidewalls of the via. The protective material facilitates shielding of at least the edges and sidewalls of the via from a trench etch step which is performed to form a trench opening in the insulating material.
Another aspect of the present invention relates to a dual damascene structure, including: an insulating material; a via formation in the insulating material; a protective layer covering at least sidewalls of the via formation; and a conductive line trench formation.
Still another aspect of the present invention relates to a dual damascene structure, including: an insulating material; a via formation in the insulating material; and means for insulating at least edges and sidewalls of the via formation from an etch step to form a conductive line trench formation.
Yet another aspect of the present invention relates to a method for fabricating interconnecting lines and vias in a layer of insulating material. A first photoresist layer is formed on the insulating material. The insulating material includes at least one of: silicon oxide (SiO), silicon dioxide (SiO
2
), silicon nitride (Si
3
N
4
), (SiN), silicon oxynitride (SiO
x
N
y
), fluonated silicon oxide (SiO
x
F
y
), and polyimide(s). The first photoresist layer is patterned to define a via The via is formed in the layer of insulating material. A protective material is formed so as to be conformal to at least edges and sidewalls of the via The protective material facilitates shielding of at least the edges and sidewalls of the via from a trench etch step. The protective material includes at least one of: a nitride and a polymer. Excess portions of the first photoresist layer and protective material are removed. A second photoresist layer is formed on the insulating material. The second photoresist layer is patterned to define a trench. The trench etch step is performed to form the trench in the insulating material. The via and trench are filled with a conductive metal.
To the accomplishment of the foregoing and related ends, the invention, then, comprises the features hereinafter fully described and particularly pointed out in the claims. The following description and the annexed drawings set forth in detail certain illustrative embodiments of the invention. These embodiments are indicative, however, of but a few of the various ways in which the principles of the invention may be employed. Other objects, advantages and novel features of the invention will become apparent from the following detailed description of the invention when considered in conjunction with the drawings.


REFERENCES:
patent: 5635423 (1997-06-01), Huang et al.
patent: 5686354 (1997-11-01), Avanzino et al.
patent: 5691238 (1997-11-01), Avanzino et al.
patent: 5693568 (1997-12-01), Liu et al.
patent: 5705430 (1998-01-01), Avanzino et al.
patent: 5795823 (1998-08-01), Avanzino et a

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