Custom logic BIST for memory controller

Details Custom logic BIST for memory controller Custom logic BIST for memory controller

2004-06-18

2009-02-24

Britt, Cynthia (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S738000, C714S742000

Reexamination Certificate

active

07496819

ABSTRACT:
A method and system for testing a memory controller are provided herein. A test sequence may be generated within the memory controller. A test output may also be generated within the memory controller, where the test output is associated with the test sequence. The test output may then be verified. The test sequence may comprise one or more of a control command, a memory address, and/or a DQM signal. The test output may be generated by a sequencer. The test output may be verified by a cyclic redundancy check (CRC) module. The test sequence may also comprise random write data. The random write data may be communicated to a memory controller write data output via a write data bus.

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