Current reduction circuit for testing purpose

Details Current reduction circuit for testing purpose Current reduction circuit for testing purpose

1997-01-07

2000-08-08

Nguyen, Hoa T.

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

714724, G01R 3128

Patent

active

061016233

ABSTRACT:
A detecting and testing circuit for detecting a leakage of current from LSI circuits mainly constituted by CMOS devices. The semiconductor integrated circuit includes a first circuit block having an output line in which a logic level responsive to an input signal is supplied through a ratio type or precharged type operation; and a first standby circuit for maintaining the first circuit block at a standby state, wherein a source of a current or electric charge is shut off from the output line on receipt of information by which the standby state is set, and respective logic levels corresponding to an arbitrary input signal is supplied to the output line of the first block circuit at a same potential level as a power supply.

REFERENCES:
patent: 4718042 (1988-01-01), Moll et al.
patent: 5019772 (1991-05-01), Dreibelbis et al.
patent: 5051995 (1991-09-01), Tobita
patent: 5388077 (1995-02-01), Sanada
patent: 5592294 (1997-01-01), Nozuyama

Affiliated with

Also associated with

Rating

Current reduction circuit for testing purpose does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Current reduction circuit for testing purpose, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Current reduction circuit for testing purpose will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1160878