Current offset sense amplifier of a modulated current or current

Details Current offset sense amplifier of a modulated current or current Current offset sense amplifier of a modulated current or current

1994-07-05

1995-10-24

Nelms, David C.

Static information storage and retrieval

Read/write circuit

For complementary information

365210, 365203, 365207, 327 56, G11C 700

Patent

active

054617138

ABSTRACT:
A circuit employing a modulated-current offset-type or current-unbalance, offset-type sense amplifier for reading programmable memory cells employs loads identical to each other and a differential input pair of transistors of the differential amplifier are "cross-coupled" with said identical loads to realize a latch structure for storing an extracted data. The circuit also employs a pair of pass transistors, and a pair of precharge transistors. The pass transistors connect the differential input transistors to a memory matrix and the precharge transistors charge lines of the memory matrix. By properly sizing and fabricating these transistors, the pass transistors connect the differential input transistors with the memory matrix while the currents provided from the precharge transistors are either nulled or minimized. The circuit utilizes three timing signals for sequentially modifying the configuration of the circuit and defining the following phases: start of a new reading cycle, pre-charging of capacitances associated with bit lines, and equalization of output nodes and line potentials, discrimination phase, reading and storing of the extracted data.

REFERENCES:
patent: 4694427 (1987-09-01), Miyamoto et al.
patent: 5138579 (1992-08-01), Tatsumi et al.
patent: 5327379 (1994-07-01), Pascucci
Gastaldi et al., "A 1-Mbit CMOS EPROM With Enhanced Verification," IEEE J. of Solid-State Circuits 23(5):1150-1156, 1988.
Kobayashi et al., "A High-Speed Parallel Sensing Architecture for Multi-Megabit Flash E.sup.2 PROM's," IEEE J. of Solid-State Circuits 25(1):79-83, 1990.

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