Current magnitude compensation for memory cells in a data...

Details Current magnitude compensation for memory cells in a data... Current magnitude compensation for memory cells in a data...

2011-08-23

2011-08-23

Le, Thong Q (Department: 2827)

Static information storage and retrieval

Systems using particular element

Resistive

C365S196000, C365S100000, C365S230060

Reexamination Certificate

active

08004875

ABSTRACT:
A data storage device and associated method for providing current magnitude compensation for memory cells in a data storage array. In accordance with some embodiments, unit cells are connected between spaced apart first and second control lines of common length. An equalization circuit is configured to respectively apply a common current magnitude through each of the unit cells by adjusting a voltage applied to the cells in relation to a location of each of the cells along the first and second control lines.

REFERENCES:
patent: 5798966 (1998-08-01), Keeney
patent: 6639824 (2003-10-01), Wohlfahrt et al.
patent: 6680865 (2004-01-01), Watanabe
patent: 7345922 (2008-03-01), Roohparvar
patent: 2009/0273961 (2009-11-01), Ono et al.

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