Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates – Field-effect transistor
Reexamination Certificate
2007-01-15
2009-08-11
Cho, James (Department: 2819)
Electronic digital logic circuitry
Clocking or synchronizing of logic stages or gates
Field-effect transistor
C326S083000, C326S112000, C326S098000
Reexamination Certificate
active
07573300
ABSTRACT:
An integrated circuit that includes a gate control voltage generator that supplies a current control gate voltage to a plurality of current control devices of a corresponding plurality of dynamic logic circuits each having a keeper circuit. The gate control voltage generator provides, via current control gate voltage, global control of the amount of keeper current flowing through the keeper circuits so as to enhance the performance of the dynamic logic circuits.
REFERENCES:
patent: 3571626 (1971-03-01), Reif
patent: 3622805 (1971-11-01), McMorrow, Jr.
patent: 3828204 (1974-08-01), Farnsworth
patent: 3879669 (1975-04-01), Moriyasu
patent: 4063119 (1977-12-01), Odell et al.
patent: 4694198 (1987-09-01), Umeki
patent: 5116342 (1992-05-01), Schmidt et al.
patent: 5144159 (1992-09-01), Frisch et al.
patent: 5336942 (1994-08-01), Khayat
patent: 5365121 (1994-11-01), Morton et al.
patent: 5703807 (1997-12-01), Smayling et al.
patent: 6002292 (1999-12-01), Allen et al.
patent: 6172555 (2001-01-01), Gusinov
patent: 6285222 (2001-09-01), Kitade
patent: 6335649 (2002-01-01), Maeda
patent: 6549040 (2003-04-01), Alvandpour et al.
patent: 6577480 (2003-06-01), Avery et al.
patent: 6756839 (2004-06-01), Hall et al.
patent: 6801060 (2004-10-01), Ikehashi et al.
patent: 7030668 (2006-04-01), Edwards
patent: 7049865 (2006-05-01), Parker et al.
patent: 7061308 (2006-06-01), Abadeer et al.
patent: 7187219 (2007-03-01), Olsen
patent: 7466171 (2008-12-01), Abadeer
patent: 2003/0122595 (2003-07-01), Hall et al.
patent: 2004/0041590 (2004-03-01), Bernstein et al.
patent: 2004/0104744 (2004-06-01), Bosshart
patent: 2004/0263208 (2004-12-01), Levy et al.
patent: 2004/0263209 (2004-12-01), Choe
patent: 2005/0073354 (2005-04-01), Abadeer et al.
patent: 2006/0170487 (2006-08-01), Abadeer
patent: 2006/0214695 (2006-09-01), Lih et al.
patent: 2006/0290385 (2006-12-01), Belluomini et al.
patent: 2008/0169839 (2008-07-01), Abadeer
patent: 2008/0169844 (2008-07-01), Abadeer
patent: 2008/0169869 (2008-07-01), Abadeer
C.H. Kim, K. Roy, S. Hsu, A. Alvandpour, R.K. Krishnamurthy, S. Borkar, “A Process Variation Compensating Technique For Sub-90 nm Dynamic Circuits,” VLSI Circuits, 2003. Digest of Technical Papers, 2003 Symposium on Jun. 12-14, 2003, pp. 205-206.
V. Kursun, E.G. Friedman, “Domino Logic With Dynamic Body Biased Keeper,” Solid-State Circuits Conference 2002, ESSCIRC 2002. Proceedings of the 28th European, Sep. 24-26, 2002, pp. 675-678.
K.E. Kuijk, “A Precision Reference Voltage Source,” IEEE Journal of Solid-State Circuits, vol. SC-8, pp. 222-226, Jun. 1973.
H. Banba, H. Shiga, A. Umezawa, T. Miyaba, T. Tanzawa, S. Atsumi, K. Sakui, “A CMOS Bandgap Reference Circuit with Sub-1-V Operation,” IEEE Journal of Solid-State Circuits, vol. 34, No. 5, May 1999, pp. 670-674.
First Office Action dated Apr. 30, 2008 with regard to related U.S. Appl. No. 11/623,114.
Response to First Office Action dated Jun. 12, 2008 with regard to U.S. Appl. No. 11/623,114.
Notice of Allowance dated Oct. 16, 2008 with regard to U.S. Appl. No. 11/623,114.
First Office Action dated Apr. 21, 2008 with regard to related U.S. Appl. No. 11/623,119.
Response to First Office Action dated May 30, 2008 with regard to related U.S. Appl. No. 11/623,119.
Notice of Allowance dated Jul. 31, 2008 with regard to related U.S. Appl. No. 11/623,119.
Related U.S. Appl. No. 11/948,308, filed Nov. 30, 2007, entitled Design Structure for a Voltage Detection Circuit in an Integrated Circuit and Method of Generating a Trigger Flag Signal; Wagdi Abadeer et al.
Related U.S. Appl. No. 12/242,114, filed Sep. 30, 2008, entitled Voltage Detection Circuit in an Integrated Circuit; Wagdi Abadeer et al.
Office Action dated May 16, 2008 with regard to related U.S. Appl. No. 11/851,133.
Amendment under 37 C.F.R. 1.111 with regard to related U.S. Appl. No. 11/851,133.
Notice of Allowance dated Jul. 31, 2008 with regard to related U.S. Appl. No. 11/851,133.
Abadeer Wagdi W.
Braceras George M.
Chu Albert M.
Fifield John A.
Pilo Harold
Cho James
Downs Rachlin & Martin PLLC
International Business Machines - Corporation
Tran Jany
LandOfFree
Current control mechanism for dynamic logic keeper circuits... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Current control mechanism for dynamic logic keeper circuits..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Current control mechanism for dynamic logic keeper circuits... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4091552