Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Signal level or switching threshold stabilization
Reexamination Certificate
2002-10-16
2004-02-10
Cho, James H. (Department: 2819)
Electronic digital logic circuitry
Signal sensitivity or transmission integrity
Signal level or switching threshold stabilization
C326S027000, C327S378000
Reexamination Certificate
active
06690192
ABSTRACT:
BACKGROUND OF INVENTION
This invention relates to output buffers, and more particularly to temperature, process, and voltage compensation for an output buffer.
Electronic systems are often constructed from integrated circuits (IC's) using s semiconductor process technology such as a complementary metal-oxide-semiconductor (CMOS) process. CMOS processes are used construct circuits of n-channel and p-channel transistors that sink or source current.
The rise and fall times of outputs of CMOS circuits are often critical parameters. When fall times are too fast, undesirable effects can occur such as ground bounce and ringing. Slow rise and fall times may be more sensitive to external noise coupled into the output. Often the rise and fall times are tightly specified to meet requirements of other circuits driven by the output.
The amount of current passing through a CMOS transistor depends on several factors, such as input and output voltages, temperature, and process variations. For example, less current is delivered at higher temperatures while more current is delivered at lower temperatures. A circuit may often be spec'ed to operate over a wide temperature range, such as 0 to 100 degrees Celsius. The current delivered can double over such a wide temperature range.
When the power-supply voltage (Vdd or Vcc) is raised, input voltages tend to rise, causing transistors to be driven by larger voltages. The higher voltages tend to produce larger currents.
While CMOS processes are carefully controlled, some variation still occurs. For example, the gate length may vary by a certain percentage, such as +/−10%, which can cause a variation in currents. Doping in transistors may vary, increasing or decreasing carrier mobility and capacitances and ultimately affecting current drive. Other process variations can be caused by a wide variety of factors that ultimately lead to current variations.
Various circuits have been devised to compensate for such voltage, temperature, and/or process variations. One common technique is to employ feedback. The output node of an output buffer can be fed back to an upstream node, causing the voltage drive to the gate of the output transistor to be modulated. When supply-voltage, temperature, and process variations cause a larger current to be delivered by the output transistor, then the output voltage changes more quickly, causing the feedback to more rapidly turn off the output transistor or reduce its gate-voltage drive and current drive. Supply voltage, temperature, and process variations that reduce output current can slow the feedback, increasing gate-voltage drive and allowing larger currents to be delivered for a longer period of time to compensate.
While such feedback compensation is useful, undesirable effects similar to oscillation can occur. Such oscillation can cause stability problems. Thus it can be desirable to not use feedback when compensating for supply-voltage, temperature, and process variations.
What is desired is a compensation circuit for a CMOS output buffer. An output buffer that compensates for supply-voltage, temperature, and process variations is desirable.
REFERENCES:
patent: 4766415 (1988-08-01), Dielacher
patent: 5994945 (1999-11-01), Wu et al.
patent: 6040737 (2000-03-01), Ranjan et al.
patent: 6535020 (2003-03-01), Yin
patent: 06164346 (1994-06-01), None
Auvinen Stuart T.
Cho James H.
Pericom Semiconductor Corp.
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